Full-precision bidirectional bit-serial convolver for real-time image processing

Lior Djaloshinski, Orly Yadid-Pecht, Ran Ginosar

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A novel chip implementing real-time image convolution is presented. The chip features a pure bit-serial architecture and systolic array structure. It consists of a 3X3 array of modular units that can be easily enlarged. The basic unit heart is a very efficient bidirectional multiplier, which can perform two different multiplications simultaneously. The chip overall size is 5.78mm X 3.18mm (in CMOS 2μ technology). It is full-precision and has a throughput of one 20 bit convolution every 10 clock cycles, with a latency of 24 clock cycles.

Original languageEnglish
Title of host publicationProceedings - 17th Convention of Electrical and Electronics Engineers in Israel, EEIS 1991
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages305-308
Number of pages4
ISBN (Electronic)0879426780, 9780879426781
DOIs
StatePublished - 1 Jan 1991
Externally publishedYes
Event17th Convention of Electrical and Electronics Engineers in Israel, EEIS 1991 - Tel Aviv, Israel
Duration: 5 Mar 19917 Mar 1991

Publication series

NameProceedings - 17th Convention of Electrical and Electronics Engineers in Israel, EEIS 1991

Conference

Conference17th Convention of Electrical and Electronics Engineers in Israel, EEIS 1991
Country/TerritoryIsrael
CityTel Aviv
Period5/03/917/03/91

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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