TY - GEN
T1 - Full-precision bidirectional bit-serial convolver for real-time image processing
AU - Djaloshinski, Lior
AU - Yadid-Pecht, Orly
AU - Ginosar, Ran
N1 - Publisher Copyright:
© Proceedings - 17th Convention of Electrical and Electronics Engineers in Israel, EEIS 1991. All rights reserved.
PY - 1991/1/1
Y1 - 1991/1/1
N2 - A novel chip implementing real-time image convolution is presented. The chip features a pure bit-serial architecture and systolic array structure. It consists of a 3X3 array of modular units that can be easily enlarged. The basic unit heart is a very efficient bidirectional multiplier, which can perform two different multiplications simultaneously. The chip overall size is 5.78mm X 3.18mm (in CMOS 2μ technology). It is full-precision and has a throughput of one 20 bit convolution every 10 clock cycles, with a latency of 24 clock cycles.
AB - A novel chip implementing real-time image convolution is presented. The chip features a pure bit-serial architecture and systolic array structure. It consists of a 3X3 array of modular units that can be easily enlarged. The basic unit heart is a very efficient bidirectional multiplier, which can perform two different multiplications simultaneously. The chip overall size is 5.78mm X 3.18mm (in CMOS 2μ technology). It is full-precision and has a throughput of one 20 bit convolution every 10 clock cycles, with a latency of 24 clock cycles.
UR - http://www.scopus.com/inward/record.url?scp=85067607371&partnerID=8YFLogxK
U2 - 10.1109/EEIS.1991.217636
DO - 10.1109/EEIS.1991.217636
M3 - Conference contribution
AN - SCOPUS:85067607371
T3 - Proceedings - 17th Convention of Electrical and Electronics Engineers in Israel, EEIS 1991
SP - 305
EP - 308
BT - Proceedings - 17th Convention of Electrical and Electronics Engineers in Israel, EEIS 1991
PB - Institute of Electrical and Electronics Engineers
T2 - 17th Convention of Electrical and Electronics Engineers in Israel, EEIS 1991
Y2 - 5 March 1991 through 7 March 1991
ER -