TY - JOUR
T1 - Full-swing gate diffusion input logic - Case-study of low-power CLA adder design
AU - Morgenshtein, Arkadiy
AU - Yuzhaninov, Viacheslav
AU - Kovshilovsky, Alexey
AU - Fish, Alexander
N1 - Funding Information:
Full Swing Gate Diffusion Input (FS GDI) methodology was proposed and evaluated on a 16 nm low power TSMC process. Simulation results showed a clear advantage of the proposed GDI CLAs by means of area, dynamic and static energy. The FS - bit Carry Look Ahead Adder (CLA). It was shown that the proposed FS - GDI circuits are beneficial in terms of performance and static power consumption, as compared to the conventional multiple Vth GDI (MVT - GDI). Three CLA versions, based on FS - GDI, MVT - GDI and standard CMOS were designed and compared in 40 - GDI achieved 2× area reduction, 5× improvement in dynamic energy dissipation and 4× decrease in leakage, with a slight (24%) degradation in performance, when compared to the CMOS CLA. Advanced design metrics of GDI cells, such as minimum energy point (MEP) operation and minimum leakage vector (MLV) were discussed. It was shown that MVT - GDI achieved better characteristics at MEP, as compared to other techniques. Arkadiy Morgenshtein received the B.Sc. degree in electrical engineering in 1999, M.Sc. in biomedical engineering in 2003, MBA in 2006 and Ph.D in electrical engineering in 2008 from Technion, Israel Institute of Technology. In 2012 he joined the IBM Haifa Research Lab. Prior to that he worked with Core CAD Technologies group at Intel Corporation, where he was researching and developing tools for power optimization and estimation at various levels of VLSI design. He has been a Teaching and Research Assistant at Electrical Engineering Department, Technion since 1999, where he is currently an Adjunct Lecturer. Dr. Morgenshtein's research interests include low-power design techniques for digital circuits, optimization of on-chip interconnect, CMOS sensors and EDA tools for power estimation and optimization. He has authored over 40 scientific papers and patent applications. Dr. Morgenshtein co-authored a paper that won the IEEE VLSI Transactions (TVLSI) Best Paper award for 2012. He was honored by Technion President's award and Intel-Technion award for excellence in study in 1998 and 2007. He supervised projects winning the award of Oz Moses Foundation by Intel in 2002 and best VLSI project in 2003 and 2005. Dr. Morgenshtein has served as associate editor for the Journal of Low Power Electronics and Applications (JLPEA), as session chairman at ICECS'04 Conference and as referee in multiple journals and conferences. Viacheslav Yuzhaninov received the B.Sc. degree in Electrical Engineering from Ben-Gurion University, Be’er Sheva, Israel, in 2012. He has been a Research Assistant at the Low Power Circuits and Systems Lab, VLSI Systems Center, Ben-Gurion University, since 2011. He is currently working on his M.Sc degree in Electrical Enginering at Bar-Ilan University. His research interests are energy effcient logic families and low voltage high performance digital design. Alexey Kovshilovsky received the B.Sc. degree in Electrical Engineering from Ben-Gurion University, Be’er Sheva, Israel, in 2012. He has been a Research Assistant at the Low Power Circuits and Systems Lab, VLSI Systems Center, Ben-Gurion University, since 2011. Currently he is working as an Embedded Software Engineer at Powermat Technologies in Neve-Ilan, Israel. Alexander Fish received the B.Sc. degree in Electrical Engineering from the Technion, Israel Institute of Technology, Haifa, Israel, in 1999. He completed his M.Sc. in 2002 and his Ph.D. (summa cum laude) in 2006, respectively, at Ben-Gurion University in Israel. He was a postdoctoral fellow in the ATIPS laboratory at the University of Calgary (Canada) from 2006–2008. In 2008 he joined the Ben-Gurion University in Israel, as a faculty member in the Electrical and Computer Engineering Department. There he founded the Low Power Circuits and Systems (LPC&S) laboratory, specializing in low power circuits and systems. In July 2011 he was appointed as a head of the VLSI Systems Center at BGU. In October 2012 Prof. Fish joined the Bar-Ilan University, Faculty of Engineering as an Associate Professor and the head of the microelectronics track. Prof. Fish also leads new Energy Efficient Electronics and Applications Labs. Prof. Fish's research interests include development of energy efficient “smart” CMOS image sensors, ultra low power SRAM, DRAM and Flash memory arrays and energy efficient design techniques for low voltage digital and analog VLSI chips. He has authored over 70 scientific papers in journals and conferences, including IEEE Journal of Solid State Circuits, IEEE Transactions on Electron Devices, IEEE Transactions on Circuits and Systems and many others. He also submitted 16 patent applications. Prof. Fish has published two book chapters. He was a co-author of papers that won the Best Paper Finalist awards at IEEE ISCAS and ICECS conferences. Prof. Fish serves as an Editor in Chief for the MDPI Journal of Low Power Electronics and Applications (JLPEA) and as an Associate Editor for the IEEE Sensors Journal. He also served as a chair of different tracks of various IEEE conferences. He was a co-organizer of many special sessions at IEEE conferences, including IEEE ISCAS, IEEE Sensors and IEEEI conferences. Prof. Fish is a member of Sensory, VLSI Systems and Applications and Bio-medical Systems Technical Committees of IEEE Circuits and Systems Society.
PY - 2014/1/1
Y1 - 2014/1/1
N2 - Full Swing Gate Diffusion Input (FS-GDI) methodology is presented. The proposed methodology is applied to a 40 nm Carry Look Ahead Adder (CLA). The CLA is implemented mainly using GDI full-swing F1 and F2 gates, which are the counterparts of standard CMOS NAND and NOR gates. A 16-bit GDI CLA was designed in a 40 nm low power TSMC process. The CLA, implemented according to the proposed methodology, presents full functionality and robustness under global and local process variations at wide range of supply voltages. Simulation results show 2× area reduction, 5× improvement in dynamic energy dissipation and 4× decrease in leakage, with a slight (24%) degradation in performance, when compared to the CMOS CLA. Advanced design metrics of GDI cells, such as minimum energy point (MEP) operation and minimum leakage vector (MLV), are discussed.
AB - Full Swing Gate Diffusion Input (FS-GDI) methodology is presented. The proposed methodology is applied to a 40 nm Carry Look Ahead Adder (CLA). The CLA is implemented mainly using GDI full-swing F1 and F2 gates, which are the counterparts of standard CMOS NAND and NOR gates. A 16-bit GDI CLA was designed in a 40 nm low power TSMC process. The CLA, implemented according to the proposed methodology, presents full functionality and robustness under global and local process variations at wide range of supply voltages. Simulation results show 2× area reduction, 5× improvement in dynamic energy dissipation and 4× decrease in leakage, with a slight (24%) degradation in performance, when compared to the CMOS CLA. Advanced design metrics of GDI cells, such as minimum energy point (MEP) operation and minimum leakage vector (MLV), are discussed.
KW - Alternative logic family
KW - Carry Look Ahead (CLA) adder
KW - Full-Swing GDI
KW - Gate Difusion Input (GDI)
KW - Low power
UR - http://www.scopus.com/inward/record.url?scp=84888117882&partnerID=8YFLogxK
U2 - 10.1016/j.vlsi.2013.04.002
DO - 10.1016/j.vlsi.2013.04.002
M3 - Article
AN - SCOPUS:84888117882
SN - 0167-9260
VL - 47
SP - 62
EP - 70
JO - Integration, the VLSI Journal
JF - Integration, the VLSI Journal
IS - 1
ER -