Gate Diffusion Input (GDI) logic in standard CMOS nanoscale process

Arkadiy Morgenshtein, Idan Shwartz, Alexander Fish

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

80 Scopus citations

Abstract

In this paper CMOS compatible Gate Diffusion Input (GDI) design technique is proposed. The GDI method enables the implementation of a wide range of complex logic functions using only two transistors. This method is suitable for the design of low-power logic gates, with a much smaller area than Static CMOS and existing PTL techniques. As opposite to our originally proposed GDI logic, the modified GDI logic is fully compatible for implementation in a standard CMOS process. Simulations of basic GDI gates under process and temperature corners in 40nm CMOS process are shown and compared to similar CMOS gates. We show that while having the same delay, GDI gates achieve leakage and active power reduction of up to 70% and 50%, respectively.

Original languageEnglish
Title of host publication2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010
Pages776-780
Number of pages5
DOIs
StatePublished - 1 Dec 2010
Event2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010 - Eilat, Israel
Duration: 17 Nov 201020 Nov 2010

Publication series

Name2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010

Conference

Conference2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010
Country/TerritoryIsrael
CityEilat
Period17/11/1020/11/10

Keywords

  • GDI
  • Gate diffusion input
  • Low power digital design
  • Pass-transistor logic

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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