@inproceedings{fc0e02cc4a7449a4a27503a282e1c2a2,
title = "Improved read access in GC-EDRAM memory by dual-negative word-line technique",
abstract = "Embedded memories occupy an increasingly dominant portion of the area and power budgets of modern SoCs and are also a limiting factor in VDD scaling. GC-eDRAM is a dense, low power option for embedded memory implementation, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires an additional boosted voltage supply for successful write operations. This work presents a novel technique that uses the same negative voltage applied to the write port in many GC-eDRAMs topologies to expedite the read operation and/or further increase the DRT by using it during read operations. An 8 kbit memory macro was implemented in a 28 nm FD-SOI technology, demonstrating over 20× read latency reduction, an order-of-magnitude longer DRT, and up-to 4 order-of-magnitude lower retention power consumption over a conventional 2T GC-eDRAM.",
keywords = "Boosted voltage, Embedded memory, GC-eDRAM, Low Power, Retention time",
author = "Roman Golman and Robert Giterman and Odem Harel and Adam Teman",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE; 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 ; Conference date: 10-10-2020 Through 21-10-2020",
year = "2020",
month = jan,
day = "1",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers",
booktitle = "2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings",
address = "United States",
}