Improvement of pipelines implementation in FPGA designs

Nonel Thirer; Yitzhak David; I. Baal Zedaka; Uzi Efron

doi:10.1117/12.678445

Improvement of pipelines implementation in FPGA designs

Nonel Thirer, Yitzhak David, I. Baal Zedaka, Uzi Efron

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

System architecture has a significant impact on software performance. In this manuscript, a method to increase the performance of the microprocessors and FPGA based systems using pipeline processing, is presented. An improved implementation using this concept, for image and display processing, providing real time vision applications, is described.

Original language	English
Title of host publication	Infrared and Photoelectronic Imagers and Detector Devices II
DOIs	https://doi.org/10.1117/12.678445
State	Published - 6 Nov 2006
Event	Infrared and Photoelectronic Imagers and Detector Devices II - San Diego, CA, United States Duration: 13 Aug 2006 → 14 Aug 2006

Publication series

Name	Proceedings of SPIE - The International Society for Optical Engineering
Volume	6294
ISSN (Print)	0277-786X

Conference

Conference	Infrared and Photoelectronic Imagers and Detector Devices II
Country/Territory	United States
City	San Diego, CA
Period	13/08/06 → 14/08/06

Keywords

FPGA design
Image transceiver
Pipeline
Superscalar
Vision

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Computer Science Applications
Applied Mathematics
Electrical and Electronic Engineering

Access to Document

10.1117/12.678445

Cite this

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title = "Improvement of pipelines implementation in FPGA designs",

abstract = "System architecture has a significant impact on software performance. In this manuscript, a method to increase the performance of the microprocessors and FPGA based systems using pipeline processing, is presented. An improved implementation using this concept, for image and display processing, providing real time vision applications, is described.",

keywords = "FPGA design, Image transceiver, Pipeline, Superscalar, Vision",

author = "Nonel Thirer and Yitzhak David and Zedaka, {I. Baal} and Uzi Efron",

year = "2006",

month = nov,

day = "6",

doi = "10.1117/12.678445",

language = "English",

isbn = "0819463736",

series = "Proceedings of SPIE - The International Society for Optical Engineering",

booktitle = "Infrared and Photoelectronic Imagers and Detector Devices II",

note = "Infrared and Photoelectronic Imagers and Detector Devices II ; Conference date: 13-08-2006 Through 14-08-2006",

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Thirer, N, David, Y, Zedaka, IB & Efron, U 2006, Improvement of pipelines implementation in FPGA designs. in Infrared and Photoelectronic Imagers and Detector Devices II., 62940T, Proceedings of SPIE - The International Society for Optical Engineering, vol. 6294, Infrared and Photoelectronic Imagers and Detector Devices II, San Diego, CA, United States, 13/08/06. https://doi.org/10.1117/12.678445

Improvement of pipelines implementation in FPGA designs. / Thirer, Nonel; David, Yitzhak; Zedaka, I. Baal et al.
Infrared and Photoelectronic Imagers and Detector Devices II. 2006. 62940T (Proceedings of SPIE - The International Society for Optical Engineering; Vol. 6294).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - David, Yitzhak

AU - Zedaka, I. Baal

AU - Efron, Uzi

PY - 2006/11/6

Y1 - 2006/11/6

N2 - System architecture has a significant impact on software performance. In this manuscript, a method to increase the performance of the microprocessors and FPGA based systems using pipeline processing, is presented. An improved implementation using this concept, for image and display processing, providing real time vision applications, is described.

AB - System architecture has a significant impact on software performance. In this manuscript, a method to increase the performance of the microprocessors and FPGA based systems using pipeline processing, is presented. An improved implementation using this concept, for image and display processing, providing real time vision applications, is described.

KW - FPGA design

KW - Image transceiver

KW - Pipeline

KW - Superscalar

KW - Vision

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M3 - Conference contribution

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SN - 0819463736

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T3 - Proceedings of SPIE - The International Society for Optical Engineering

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Y2 - 13 August 2006 through 14 August 2006

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Improvement of pipelines implementation in FPGA designs

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

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