In-Device SEM-Based Overlay Metrology on VIA Layer of Logic Process

Sheng Huang; Wei Zhu; Dennis Wang; Allen Wu; Chao Zhou; Qingpeng Zhu; Runzhi Wang; Jiawang Song; Wensheng Li; Or Zruya; Lee Rubinstein; Amir Rosen

doi:10.1109/CSTIC64481.2025.11017840

In-Device SEM-Based Overlay Metrology on VIA Layer of Logic Process

Sheng Huang
, Wei Zhu
, Dennis Wang
, Allen Wu
, Chao Zhou
, Qingpeng Zhu
, Runzhi Wang
, Jiawang Song
, Wensheng Li
, Or Zruya
, Lee Rubinstein
, Amir Rosen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Device shrinkage requires continuous tightening of the overlay (OVL) control. Systematic deviation between optical after-develop inspection (ADI) and after-etch inspection (AEI) OVL, known as non-zero offset (NZO), is critically important when applied to the scanner process. In the 28 nm logic process, the VIA layer relies on accurate OVL control to ensure device yield. In this paper, we discuss in-device SEM-based OVL metrology of the VIA layer to demonstrate the NZO gap and enable a better corrective methodology to minimize NZO in the advanced process control (APC) loop. In addition, the SEM OVL is valuable for providing more detailed and comprehensive OVL distributions, enabling high-order correction of the scanner process.

Original language	English
Title of host publication	2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025
Editors	Cor Claeys, Beichao Zhang, Beichao Zhang, Bin Yu, Peng Bai, Qianqian Huang, Xiaowei Li, Steve X. Liang, Hsiang-Lan Lung, Linyong Pang, Weikang Qian, Xinping Qu, Xiaoping Shi, Jianshi Tang, Ying Zhang, Pingqiang Zhou, Cheng Zhuo
Publisher	Institute of Electrical and Electronics Engineers
ISBN (Electronic)	9798331513351
DOIs	https://doi.org/10.1109/CSTIC64481.2025.11017840
State	Published - 1 Jan 2025
Externally published	Yes
Event	2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025 - Shanghai, China Duration: 24 May 2025 → 25 May 2025

Publication series

Name	2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025

Conference

Conference	2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025
Country/Territory	China
City	Shanghai
Period	24/05/25 → 25/05/25

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Artificial Intelligence
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/CSTIC64481.2025.11017840

Cite this

Huang, S., Zhu, W., Wang, D., Wu, A., Zhou, C., Zhu, Q., Wang, R., Song, J., Li, W., Zruya, O., Rubinstein, L., & Rosen, A. (2025). In-Device SEM-Based Overlay Metrology on VIA Layer of Logic Process. In C. Claeys, B. Zhang, B. Zhang, B. Yu, P. Bai, Q. Huang, X. Li, S. X. Liang, H.-L. Lung, L. Pang, W. Qian, X. Qu, X. Shi, J. Tang, Y. Zhang, P. Zhou, & C. Zhuo (Eds.), 2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025 (2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/CSTIC64481.2025.11017840

Huang, Sheng ; Zhu, Wei ; Wang, Dennis et al. / In-Device SEM-Based Overlay Metrology on VIA Layer of Logic Process. 2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025. editor / Cor Claeys ; Beichao Zhang ; Beichao Zhang ; Bin Yu ; Peng Bai ; Qianqian Huang ; Xiaowei Li ; Steve X. Liang ; Hsiang-Lan Lung ; Linyong Pang ; Weikang Qian ; Xinping Qu ; Xiaoping Shi ; Jianshi Tang ; Ying Zhang ; Pingqiang Zhou ; Cheng Zhuo. Institute of Electrical and Electronics Engineers, 2025. (2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025).

@inproceedings{7159b08d54874cf895135abae0e0ae3d,

title = "In-Device SEM-Based Overlay Metrology on VIA Layer of Logic Process",

abstract = "Device shrinkage requires continuous tightening of the overlay (OVL) control. Systematic deviation between optical after-develop inspection (ADI) and after-etch inspection (AEI) OVL, known as non-zero offset (NZO), is critically important when applied to the scanner process. In the 28 nm logic process, the VIA layer relies on accurate OVL control to ensure device yield. In this paper, we discuss in-device SEM-based OVL metrology of the VIA layer to demonstrate the NZO gap and enable a better corrective methodology to minimize NZO in the advanced process control (APC) loop. In addition, the SEM OVL is valuable for providing more detailed and comprehensive OVL distributions, enabling high-order correction of the scanner process.",

author = "Sheng Huang and Wei Zhu and Dennis Wang and Allen Wu and Chao Zhou and Qingpeng Zhu and Runzhi Wang and Jiawang Song and Wensheng Li and Or Zruya and Lee Rubinstein and Amir Rosen",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025 ; Conference date: 24-05-2025 Through 25-05-2025",

year = "2025",

month = jan,

day = "1",

doi = "10.1109/CSTIC64481.2025.11017840",

language = "English",

series = "2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025",

publisher = "Institute of Electrical and Electronics Engineers",

editor = "Cor Claeys and Beichao Zhang and Beichao Zhang and Bin Yu and Peng Bai and Qianqian Huang and Xiaowei Li and Liang, \{Steve X.\} and Hsiang-Lan Lung and Linyong Pang and Weikang Qian and Xinping Qu and Xiaoping Shi and Jianshi Tang and Ying Zhang and Pingqiang Zhou and Cheng Zhuo",

booktitle = "2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025",

address = "United States",

}

Huang, S, Zhu, W, Wang, D, Wu, A, Zhou, C, Zhu, Q, Wang, R, Song, J, Li, W, Zruya, O, Rubinstein, L & Rosen, A 2025, In-Device SEM-Based Overlay Metrology on VIA Layer of Logic Process. in C Claeys, B Zhang, B Zhang, B Yu, P Bai, Q Huang, X Li, SX Liang, H-L Lung, L Pang, W Qian, X Qu, X Shi, J Tang, Y Zhang, P Zhou & C Zhuo (eds), 2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025. 2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025, Institute of Electrical and Electronics Engineers, 2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025, Shanghai, China, 24/05/25. https://doi.org/10.1109/CSTIC64481.2025.11017840

In-Device SEM-Based Overlay Metrology on VIA Layer of Logic Process. / Huang, Sheng; Zhu, Wei; Wang, Dennis et al.
2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025. ed. / Cor Claeys; Beichao Zhang; Beichao Zhang; Bin Yu; Peng Bai; Qianqian Huang; Xiaowei Li; Steve X. Liang; Hsiang-Lan Lung; Linyong Pang; Weikang Qian; Xinping Qu; Xiaoping Shi; Jianshi Tang; Ying Zhang; Pingqiang Zhou; Cheng Zhuo. Institute of Electrical and Electronics Engineers, 2025. (2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - In-Device SEM-Based Overlay Metrology on VIA Layer of Logic Process

AU - Huang, Sheng

AU - Zhu, Wei

AU - Wang, Dennis

AU - Wu, Allen

AU - Zhou, Chao

AU - Zhu, Qingpeng

AU - Wang, Runzhi

AU - Song, Jiawang

AU - Li, Wensheng

AU - Zruya, Or

AU - Rubinstein, Lee

AU - Rosen, Amir

PY - 2025/1/1

Y1 - 2025/1/1

N2 - Device shrinkage requires continuous tightening of the overlay (OVL) control. Systematic deviation between optical after-develop inspection (ADI) and after-etch inspection (AEI) OVL, known as non-zero offset (NZO), is critically important when applied to the scanner process. In the 28 nm logic process, the VIA layer relies on accurate OVL control to ensure device yield. In this paper, we discuss in-device SEM-based OVL metrology of the VIA layer to demonstrate the NZO gap and enable a better corrective methodology to minimize NZO in the advanced process control (APC) loop. In addition, the SEM OVL is valuable for providing more detailed and comprehensive OVL distributions, enabling high-order correction of the scanner process.

AB - Device shrinkage requires continuous tightening of the overlay (OVL) control. Systematic deviation between optical after-develop inspection (ADI) and after-etch inspection (AEI) OVL, known as non-zero offset (NZO), is critically important when applied to the scanner process. In the 28 nm logic process, the VIA layer relies on accurate OVL control to ensure device yield. In this paper, we discuss in-device SEM-based OVL metrology of the VIA layer to demonstrate the NZO gap and enable a better corrective methodology to minimize NZO in the advanced process control (APC) loop. In addition, the SEM OVL is valuable for providing more detailed and comprehensive OVL distributions, enabling high-order correction of the scanner process.

UR - https://www.scopus.com/pages/publications/105008437010

U2 - 10.1109/CSTIC64481.2025.11017840

DO - 10.1109/CSTIC64481.2025.11017840

M3 - Conference contribution

AN - SCOPUS:105008437010

T3 - 2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025

BT - 2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025

A2 - Claeys, Cor

A2 - Zhang, Beichao

A2 - Yu, Bin

A2 - Bai, Peng

A2 - Huang, Qianqian

A2 - Li, Xiaowei

A2 - Liang, Steve X.

A2 - Lung, Hsiang-Lan

A2 - Pang, Linyong

A2 - Qian, Weikang

A2 - Qu, Xinping

A2 - Shi, Xiaoping

A2 - Tang, Jianshi

A2 - Zhang, Ying

A2 - Zhou, Pingqiang

A2 - Zhuo, Cheng

PB - Institute of Electrical and Electronics Engineers

T2 - 2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025

Y2 - 24 May 2025 through 25 May 2025

ER -

Huang S, Zhu W, Wang D, Wu A, Zhou C, Zhu Q et al. In-Device SEM-Based Overlay Metrology on VIA Layer of Logic Process. In Claeys C, Zhang B, Zhang B, Yu B, Bai P, Huang Q, Li X, Liang SX, Lung HL, Pang L, Qian W, Qu X, Shi X, Tang J, Zhang Y, Zhou P, Zhuo C, editors, 2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025. Institute of Electrical and Electronics Engineers. 2025. (2025 Conference of Science and Technology of Integrated Circuits, CSTIC 2025). doi: 10.1109/CSTIC64481.2025.11017840

In-Device SEM-Based Overlay Metrology on VIA Layer of Logic Process

Abstract

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ASJC Scopus subject areas

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