Inclusive Performance Analysis of 100 Gbps PAM-4 at SerDes Using Digital Equalizers

  • Gilad Katz
  • , Stiven Zlotsky
  • , Ido Vinitzky
  • , Alon Babecovand
  • , Benjamin Wolftson
  • , Eduard Sonkin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In recent years, we have witnessed an increase in data transfer rates, which requires the development of new communication methods that can handle high-speed data transfer at challenging communication channels. One of the needs is the transmission of communication over serializer deserializer (SerDes) printed circuit boards (PCBs). which are used to transmit data between chips at high speeds of 10 Gbps and above, using the pulse amplitude modulation with four levels (PAM-4) encoding method, which enables lower losses and relatively low cost. Significant signal degradation is present in high-speed communication systems at SerDes, and inter-symbol interference (ISI) distortion dominates. One of the most effective methods to mitigate ISI distortion is the use of equalizers. The goal of this research is to study the performance of communication between two chips (transmitter/receiver) over SerDes PCB at 100 Gbps using the PAM-4 encoding method with an integrated continuous time linear equalizer (CTLE), feedforward equalizer (FFE), and decision feedback equalizer (DFE). The analysis includes a transmitter/receiver with PAM-4 encoding including the PCB channel response. Further, testing the performance of the combination of different equalizers while defining relevant values and parameters (rate, transmission, convergence rate, and equalizer coefficients). Performance are evaluated using signal-to-noise ratio (SNR) and bit error rate (BER) metrics. We investigated the BER performance for five PCBs of different lengths with analog CTLE and digital FFE-DFE equalizers and found that: For a small number of taps in FFE-DFE, a specific CTLE configuration is optimal, but for an optimal combination of FFEDFE, a different configuration of the CTLE is the best for all PCB lengths. We also show that the longer the PCB length, the more coefficients of the FFE-DFE are needed, consequently, more power is required to compensate for a longer PCB length. The components of your paper [title, text, heads, etc.] are already defined in its style sheet. *CAUTION: Do Not Use Symbols, Special Characters, Footnotes, or Math in Paper Title or Abstract.

Original languageEnglish
Title of host publication2024 Asian Conference on Communication and Networks, ASIANComNet 2024
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Electronic)9798350367003
DOIs
StatePublished - 1 Jan 2024
Externally publishedYes
Event1st Asian Conference on Communication and Networks, ASIANComNet 2024 - Hybrid, Bangkok, Thailand
Duration: 24 Oct 202427 Oct 2024

Publication series

Name2024 Asian Conference on Communication and Networks, ASIANComNet 2024

Conference

Conference1st Asian Conference on Communication and Networks, ASIANComNet 2024
Country/TerritoryThailand
CityHybrid, Bangkok
Period24/10/2427/10/24

Keywords

  • CTLE
  • DSP
  • Equalization
  • PAM-4
  • PCB
  • SerDes

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Networks and Communications
  • Safety, Risk, Reliability and Quality
  • Control and Optimization

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