Integrating Critical Queue Time Constraints into SMT2020 Simulation Models

Denny Kopp; Michael Hassoun; Adar Kalir; Lars Monch

doi:10.1109/WSC48552.2020.9383889

Integrating Critical Queue Time Constraints into SMT2020 Simulation Models

Denny Kopp, Michael Hassoun, Adar Kalir, Lars Monch

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, we study the impact of critical queue time (CQT) constraints in semiconductor wafer fabrication facilities (wafer fabs). Process engineers impose CQT constraints that require wafers to start a subsequent operation within a given time window after a certain operation is completed to prevent native oxidation and contamination effects on the wafer surface. We equip dataset 2 of the SMT2020 testbed with production control logic to avoid CQT constraint violations. Therefore, two different CQT-aware dispatching rules and a combination of a lot stopping strategy with these rules are proposed. The effect of the production control strategies is investigated by means of a simulation study. We show that the number of CQT violations can be reduced without large deteriorations of global performance measures such as cycle time and throughput.

Original language	English
Title of host publication	Proceedings of the 2020 Winter Simulation Conference, WSC 2020
Editors	K.-H. Bae, B. Feng, S. Kim, S. Lazarova-Molnar, Z. Zheng, T. Roeder, R. Thiesing
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1813-1824
Number of pages	12
ISBN (Electronic)	9781728194998
DOIs	https://doi.org/10.1109/WSC48552.2020.9383889
State	Published - 14 Dec 2020
Externally published	Yes
Event	2020 Winter Simulation Conference, WSC 2020 - Orlando, United States Duration: 14 Dec 2020 → 18 Dec 2020

Publication series

Name	Proceedings - Winter Simulation Conference
Volume	2020-December
ISSN (Print)	0891-7736

Conference

Conference	2020 Winter Simulation Conference, WSC 2020
Country/Territory	United States
City	Orlando
Period	14/12/20 → 18/12/20

Access to Document

10.1109/WSC48552.2020.9383889

Cite this

Kopp, D., Hassoun, M., Kalir, A., & Monch, L. (2020). Integrating Critical Queue Time Constraints into SMT2020 Simulation Models. In K-H. Bae, B. Feng, S. Kim, S. Lazarova-Molnar, Z. Zheng, T. Roeder, & R. Thiesing (Eds.), Proceedings of the 2020 Winter Simulation Conference, WSC 2020 (pp. 1813-1824). [9383889] (Proceedings - Winter Simulation Conference; Vol. 2020-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/WSC48552.2020.9383889

Kopp, Denny ; Hassoun, Michael ; Kalir, Adar ; Monch, Lars. / Integrating Critical Queue Time Constraints into SMT2020 Simulation Models. Proceedings of the 2020 Winter Simulation Conference, WSC 2020. editor / K.-H. Bae ; B. Feng ; S. Kim ; S. Lazarova-Molnar ; Z. Zheng ; T. Roeder ; R. Thiesing. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 1813-1824 (Proceedings - Winter Simulation Conference).

@inproceedings{588a18a1c46543a390a5d7f803000786,

title = "Integrating Critical Queue Time Constraints into SMT2020 Simulation Models",

abstract = "In this paper, we study the impact of critical queue time (CQT) constraints in semiconductor wafer fabrication facilities (wafer fabs). Process engineers impose CQT constraints that require wafers to start a subsequent operation within a given time window after a certain operation is completed to prevent native oxidation and contamination effects on the wafer surface. We equip dataset 2 of the SMT2020 testbed with production control logic to avoid CQT constraint violations. Therefore, two different CQT-aware dispatching rules and a combination of a lot stopping strategy with these rules are proposed. The effect of the production control strategies is investigated by means of a simulation study. We show that the number of CQT violations can be reduced without large deteriorations of global performance measures such as cycle time and throughput.",

author = "Denny Kopp and Michael Hassoun and Adar Kalir and Lars Monch",

note = "Funding Information: The research was partially supported by the iDev 4.0 project. The iDev40 project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 783163. The JU receives support from the European Union{\textquoteright}s Horizon 2020 research and innovation programme. It is co-funded by the consortium members, grants from Austria, Germany, Belgium, Italy, Spain and Romania. The authors gratefully acknowledge this financial support. Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 Winter Simulation Conference, WSC 2020 ; Conference date: 14-12-2020 Through 18-12-2020",

year = "2020",

month = dec,

day = "14",

doi = "10.1109/WSC48552.2020.9383889",

language = "English",

series = "Proceedings - Winter Simulation Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1813--1824",

editor = "K.-H. Bae and B. Feng and S. Kim and S. Lazarova-Molnar and Z. Zheng and T. Roeder and R. Thiesing",

booktitle = "Proceedings of the 2020 Winter Simulation Conference, WSC 2020",

address = "United States",

}

Kopp, D, Hassoun, M, Kalir, A & Monch, L 2020, Integrating Critical Queue Time Constraints into SMT2020 Simulation Models. in K-H Bae, B Feng, S Kim, S Lazarova-Molnar, Z Zheng, T Roeder & R Thiesing (eds), Proceedings of the 2020 Winter Simulation Conference, WSC 2020., 9383889, Proceedings - Winter Simulation Conference, vol. 2020-December, Institute of Electrical and Electronics Engineers Inc., pp. 1813-1824, 2020 Winter Simulation Conference, WSC 2020, Orlando, United States, 14/12/20. https://doi.org/10.1109/WSC48552.2020.9383889

Integrating Critical Queue Time Constraints into SMT2020 Simulation Models. / Kopp, Denny; Hassoun, Michael; Kalir, Adar; Monch, Lars.

Proceedings of the 2020 Winter Simulation Conference, WSC 2020. ed. / K.-H. Bae; B. Feng; S. Kim; S. Lazarova-Molnar; Z. Zheng; T. Roeder; R. Thiesing. Institute of Electrical and Electronics Engineers Inc., 2020. p. 1813-1824 9383889 (Proceedings - Winter Simulation Conference; Vol. 2020-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Integrating Critical Queue Time Constraints into SMT2020 Simulation Models

AU - Kopp, Denny

AU - Hassoun, Michael

AU - Kalir, Adar

AU - Monch, Lars

N1 - Funding Information: The research was partially supported by the iDev 4.0 project. The iDev40 project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 783163. The JU receives support from the European Union’s Horizon 2020 research and innovation programme. It is co-funded by the consortium members, grants from Austria, Germany, Belgium, Italy, Spain and Romania. The authors gratefully acknowledge this financial support. Publisher Copyright: © 2020 IEEE.

PY - 2020/12/14

Y1 - 2020/12/14

N2 - In this paper, we study the impact of critical queue time (CQT) constraints in semiconductor wafer fabrication facilities (wafer fabs). Process engineers impose CQT constraints that require wafers to start a subsequent operation within a given time window after a certain operation is completed to prevent native oxidation and contamination effects on the wafer surface. We equip dataset 2 of the SMT2020 testbed with production control logic to avoid CQT constraint violations. Therefore, two different CQT-aware dispatching rules and a combination of a lot stopping strategy with these rules are proposed. The effect of the production control strategies is investigated by means of a simulation study. We show that the number of CQT violations can be reduced without large deteriorations of global performance measures such as cycle time and throughput.

AB - In this paper, we study the impact of critical queue time (CQT) constraints in semiconductor wafer fabrication facilities (wafer fabs). Process engineers impose CQT constraints that require wafers to start a subsequent operation within a given time window after a certain operation is completed to prevent native oxidation and contamination effects on the wafer surface. We equip dataset 2 of the SMT2020 testbed with production control logic to avoid CQT constraint violations. Therefore, two different CQT-aware dispatching rules and a combination of a lot stopping strategy with these rules are proposed. The effect of the production control strategies is investigated by means of a simulation study. We show that the number of CQT violations can be reduced without large deteriorations of global performance measures such as cycle time and throughput.

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M3 - Conference contribution

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T3 - Proceedings - Winter Simulation Conference

SP - 1813

EP - 1824

BT - Proceedings of the 2020 Winter Simulation Conference, WSC 2020

A2 - Bae, K.-H.

A2 - Feng, B.

A2 - Kim, S.

A2 - Lazarova-Molnar, S.

A2 - Zheng, Z.

A2 - Roeder, T.

A2 - Thiesing, R.

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 Winter Simulation Conference, WSC 2020

Y2 - 14 December 2020 through 18 December 2020

ER -

Kopp D, Hassoun M, Kalir A, Monch L. Integrating Critical Queue Time Constraints into SMT2020 Simulation Models. In Bae K-H, Feng B, Kim S, Lazarova-Molnar S, Zheng Z, Roeder T, Thiesing R, editors, Proceedings of the 2020 Winter Simulation Conference, WSC 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 1813-1824. 9383889. (Proceedings - Winter Simulation Conference). https://doi.org/10.1109/WSC48552.2020.9383889

Integrating Critical Queue Time Constraints into SMT2020 Simulation Models

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