@inproceedings{a91afc1c3e05487aa770ea1d2fe63b79,
title = "Live Demo: Silicon evaluation of multimode dual mode logic for PVT-aware datapaths",
abstract = "This demo demonstrates the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from − 40 ° C to 125 ° C confirmed the effectiveness of the proposed approach to compensate even for severe process, voltage and temperature (PVT) variations.",
author = "Inbal Stanger and Netanel Shavit and Ramiro Taco and Marco Lanuzza and Alexander Fish",
note = "Publisher Copyright: {\textcopyright} 2021 IEEE; 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 ; Conference date: 22-05-2021 Through 28-05-2021",
year = "2021",
month = jan,
day = "1",
doi = "10.1109/ISCAS51556.2021.9401425",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers",
booktitle = "2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings",
address = "United States",
}