Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to traditional SRAM, due to its high-density, low-leakage, and inherent 2-ported operation, yet, its dynamic nature leads to limited retention time that requires periodic, power-hungry refresh cycles. However, the emerging approximate computing paradigm utilizes the inherent error resilience of some applications to tolerate data errors. Such error tolerance can be exploited by reducing the refresh rate in GC-eDRAM to achieve a substantial decrease in power consumption, at the cost of an increase in cell failure probability. In this demonstration, we present the first fabricated and fully functional GC-eDRAM in a 28 nm bulk CMOS technology. The array, which is based on a novel mixed-VT 4T bitcell, can be used in both traditional and for approximate computing applications, featuring a small silicon footprint and supporting high-performance operation. Silicon measurements demonstrate successful operation at 800 Mhz under a 900 mV supply, while retaining almost 30% lower area than a single-ported 6T SRAM in the same technology.