Low-power partial-parallel Chien search architecture with polynomial degree reduction

The Chien search for the error locator polynomial root computation in BCH and Reed-Solomon decoding accounts for a significant part of the overall decoder power consumption, especially r long codes over finite fields of high order. For serial Chien search, the power consumption is substantially lowered by a polynomial degree reduction (PDR) scheme. Every time a root is found, it is factored out of the error locator polynomial. Only the hardware units associated with the reduced-degree polynomial coefficients are active. However, this PDR scheme can not be directly extended to partial-parallel Chien search, which is needed in any systems to achieve high throughput. By analyzing the formulas of the evaluation values over finite field elements and available intermediate results of the Chien search, this paper proposes a partial-parallel Chien search architecture that reduces the error locator polynomial degree on the fly whenever a root is found without using long division. For a 122-error-correcting BCH code over GF(215), an 8-parallel Chien search using the proposed architecture achieves 32% power reduction over existing partial-parallel architectures for a typical case.