Low voltage dual mode logic: Model analysis and parameter extraction

I. Levi, A. Kaizerman, A. Fish

Research output: Contribution to journalArticlepeer-review

26 Scopus citations

Abstract

The Dual Model Logic (DML) family, which was recently introduced by our group for sub-threshold operation, provides an alternative design methodology to the existing low power digital design techniques. DML gates allow switching between static and dynamic modes of operation on-the-fly according to system requirements, presenting better tradeoff between Energy consumption and performance. In static mode, low voltage DML gates achieve very low Energy consumption with moderate performance, while in dynamic mode they achieve high performance, albeit with higher Energy consumption. In this paper we analyze DML gates operation in the sub- and near-threshold regions by employing a recently proposed transregional model for low supply voltages. The sizing methodology of low voltage DML is discussed and classical Logical Effort parameters are calculated for the 40 nm DML basic gates. The design example of a DML full adder, implemented in a 40 nm low power standard CMOS technology, is shown to compare the proposed method with its CMOS and Domino counterparts. Monte Carlo simulations are shown to demonstrate the DML immunity to process variations.

Original languageEnglish
Pages (from-to)553-560
Number of pages8
JournalMicroelectronics Journal
Volume44
Issue number6
DOIs
StatePublished - 1 Jun 2013

Keywords

  • DML
  • Dual mode logic
  • Low power
  • Low voltage logic

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

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