Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI

Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish

Research output: Contribution to journalArticlepeer-review

38 Scopus citations

Abstract

In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for low voltage logic design in state-of-the-art 28 nm ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The inherent benefits of the low-granularity body-bias control, provided by the GLBB approach, are emphasized by the efficiency of forward body bias (FBB) in the FD-SOI technology. In addition, the possibility to integrate PMOS and NMOS devices into a single common well configuration allows significant area reduction, as compared to an equivalent triple well implementation. Some arithmetic circuits were designed using GLBB approach and compared to their conventional CMOS and DTMOS counterparts under different running conditions at low voltage regime. Simulation results shows that, for 300 mV of supply voltage, a 4 × 4-bit GLBB Baugh Wooley multiplier allows performance improvement of about 30% and area reduction of about 35%, while maintaining low energy consumption as compared to the conventional CMOs\DTMOS solutions. Performance and energy benefits are maintained over a wide range of process-voltage-temperature (PVT) variations.

Original languageEnglish
Pages (from-to)185-192
Number of pages8
JournalSolid-State Electronics
Volume117
DOIs
StatePublished - 1 Mar 2016
Externally publishedYes

Keywords

  • Dynamic body biasing
  • Low-voltage logic design
  • UTBB FD-SOI

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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