@inproceedings{f1ac9a68f401497789719119953fdc2c,
title = "Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI",
abstract = "In this paper, a low voltage ripple-carry adder (RCA), designed for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology, is proposed. The circuit synergistically benefits from low-granularity back-bias control to improve performance in conjunction with the integration of both NMOS and PMOS devices into a common well configuration which allows highly efficient area utilization. The design was compared over standard CMOS and DTMOS solutions. Comparative post-layout results demonstrate that the suggested approach improves energy consumption up to 57% in comparison to the equivalent DTMOS design and reduces delay up to 30% with similar energy consumption, when compared to the conventional CMOS implementation. In addition, reduced silicon area occupancy is achieved.",
keywords = "FD-SOI, gate-level body biasing, single well",
author = "Ramiro Taco and Itamar Levi and Marco Lanuzza and Alexander Fish",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 ; Conference date: 05-10-2015 Through 08-10-2015",
year = "2015",
month = nov,
day = "20",
doi = "10.1109/S3S.2015.7333515",
language = "English",
series = "2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015",
publisher = "Institute of Electrical and Electronics Engineers",
booktitle = "2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015",
address = "United States",
}
