Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI

Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

In this paper, a low voltage ripple-carry adder (RCA), designed for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology, is proposed. The circuit synergistically benefits from low-granularity back-bias control to improve performance in conjunction with the integration of both NMOS and PMOS devices into a common well configuration which allows highly efficient area utilization. The design was compared over standard CMOS and DTMOS solutions. Comparative post-layout results demonstrate that the suggested approach improves energy consumption up to 57% in comparison to the equivalent DTMOS design and reduces delay up to 30% with similar energy consumption, when compared to the conventional CMOS implementation. In addition, reduced silicon area occupancy is achieved.

Original languageEnglish
Title of host publication2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509002597
DOIs
StatePublished - 20 Nov 2015
Externally publishedYes
EventIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 - Rohnert Park, United States
Duration: 5 Oct 20158 Oct 2015

Publication series

Name2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

Conference

ConferenceIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
Country/TerritoryUnited States
CityRohnert Park
Period5/10/158/10/15

Keywords

  • FD-SOI
  • gate-level body biasing
  • single well

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