Recent research has shown that minimum energy operation of digital circuits is in the sub-threshold region, and a good trade-off between power and performance can be achieved through operation at near threshold supply voltages. However, due to process variations and device mismatch at nanoscale technology nodes, voltage scaling of standard SRAMs is limited to strong-inversion operation. One of the techniques for enabling operation at low voltages is implementation of a Supply Feedback mechanism that internally weakens the pull-up current during write operations. This concept was recently implemented in a 9T Supply Feedback SRAM (SF-SRAM) cell, fabricated and successfully tested in a 40nm CMOS technology. In this paper, we review existing low voltage SRAM solutions, overview the SF-SRAM cell, and show its scalability into deep nanoscale technologies by using the 22nm predictive model.