Medium voltage multi-level inverters: Hardware-in-the-loop (HIL) simulations

Raul Rabinovici; Dmitriy Tokar; Dmitry Baimel

doi:10.1109/EEEI.2012.6377130

Medium voltage multi-level inverters: Hardware-in-the-loop (HIL) simulations

Raul Rabinovici, Dmitriy Tokar, Dmitry Baimel

Department of Electrical & Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents low cost flexible FPGA based HIL simulator and HIL simulation results for 5, 9, and 13-level topologies of medium voltage multi-level inverters that controlled by carrier based pulse-width-modulation (PWM) algorithm. The applications of these inverters can be synchronous or induction motors. The HIL simulation results for each topology are introduced and compared to the conventional simulation results in concept of the load current total harmonic distortion (THD). In addition, the influence of control parameters such as frequency modulation ration, amplitude modulation ration and phase shift between carrier and modulation signals on the load current THD in the HIL simulator is analyzed, and the optimal parameters are introduced.

Original language	English
Title of host publication	2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012
DOIs	https://doi.org/10.1109/EEEI.2012.6377130
State	Published - 1 Dec 2012
Event	2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012 - Eilat, Israel Duration: 14 Nov 2012 → 17 Nov 2012

Publication series

Name	2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012

Conference

Conference	2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012
Country/Territory	Israel
City	Eilat
Period	14/11/12 → 17/11/12

Keywords

Hardware-in-the-loop (HIL)
field programmable gate array (FPGA)
neutral point clamped (NPC) inverter
real-time (RT)

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/EEEI.2012.6377130

Cite this

@inproceedings{29f8d64b6e5d460592b816d91a6427a0,

title = "Medium voltage multi-level inverters: Hardware-in-the-loop (HIL) simulations",

abstract = "This paper presents low cost flexible FPGA based HIL simulator and HIL simulation results for 5, 9, and 13-level topologies of medium voltage multi-level inverters that controlled by carrier based pulse-width-modulation (PWM) algorithm. The applications of these inverters can be synchronous or induction motors. The HIL simulation results for each topology are introduced and compared to the conventional simulation results in concept of the load current total harmonic distortion (THD). In addition, the influence of control parameters such as frequency modulation ration, amplitude modulation ration and phase shift between carrier and modulation signals on the load current THD in the HIL simulator is analyzed, and the optimal parameters are introduced.",

keywords = "Hardware-in-the-loop (HIL), field programmable gate array (FPGA), neutral point clamped (NPC) inverter, real-time (RT)",

author = "Raul Rabinovici and Dmitriy Tokar and Dmitry Baimel",

year = "2012",

month = dec,

day = "1",

doi = "10.1109/EEEI.2012.6377130",

language = "English",

isbn = "9781467346801",

series = "2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012",

booktitle = "2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012",

note = "2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012 ; Conference date: 14-11-2012 Through 17-11-2012",

}

Rabinovici, R, Tokar, D & Baimel, D 2012, Medium voltage multi-level inverters: Hardware-in-the-loop (HIL) simulations. in 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012., 6377130, 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012, 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012, Eilat, Israel, 14/11/12. https://doi.org/10.1109/EEEI.2012.6377130

Medium voltage multi-level inverters: Hardware-in-the-loop (HIL) simulations. / Rabinovici, Raul; Tokar, Dmitriy; Baimel, Dmitry.
2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012. 2012. 6377130 (2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents low cost flexible FPGA based HIL simulator and HIL simulation results for 5, 9, and 13-level topologies of medium voltage multi-level inverters that controlled by carrier based pulse-width-modulation (PWM) algorithm. The applications of these inverters can be synchronous or induction motors. The HIL simulation results for each topology are introduced and compared to the conventional simulation results in concept of the load current total harmonic distortion (THD). In addition, the influence of control parameters such as frequency modulation ration, amplitude modulation ration and phase shift between carrier and modulation signals on the load current THD in the HIL simulator is analyzed, and the optimal parameters are introduced.

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KW - neutral point clamped (NPC) inverter

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Medium voltage multi-level inverters: Hardware-in-the-loop (HIL) simulations

Abstract

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Keywords

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