TY - GEN
T1 - Minimum DC Link Capacitance for a Family of Three-Phase Three-Level Grid-Connected Converters Operating with Arbitrary Power Factor
AU - Siton, Yarden
AU - Mellincovsky, Martin
AU - Kuperman, Alon
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024/1/1
Y1 - 2024/1/1
N2 - This paper introduces an approach to calculating the minimum value of split DC link capacitance in three-phase three-level grid-connected DC-AC converters operating with arbitrary power factor without either active balancing circuits or AC zero sequence injection. Due to the fact that partial DC link voltages and rectified mains phase voltages reach their maximum and minimum values, respectively, at different time instants, it is feasible to decrease the minimum value of the former below the maximum value of the latter while still maintaining proper functionality of the power stage. The minimum possible split DC link capacitance values are hence derived from the boundary condition where the above-mentioned voltages are tangent to each other. The accuracy of the analytical derivations is confirmed by simulations using PSIM software, which show a high degree of agreement.
AB - This paper introduces an approach to calculating the minimum value of split DC link capacitance in three-phase three-level grid-connected DC-AC converters operating with arbitrary power factor without either active balancing circuits or AC zero sequence injection. Due to the fact that partial DC link voltages and rectified mains phase voltages reach their maximum and minimum values, respectively, at different time instants, it is feasible to decrease the minimum value of the former below the maximum value of the latter while still maintaining proper functionality of the power stage. The minimum possible split DC link capacitance values are hence derived from the boundary condition where the above-mentioned voltages are tangent to each other. The accuracy of the analytical derivations is confirmed by simulations using PSIM software, which show a high degree of agreement.
KW - split DC link capacitance
KW - three-phase three-level converters
KW - zero-sequence
UR - http://www.scopus.com/inward/record.url?scp=85201548577&partnerID=8YFLogxK
U2 - 10.1109/CPE-POWERENG60842.2024.10604320
DO - 10.1109/CPE-POWERENG60842.2024.10604320
M3 - Conference contribution
AN - SCOPUS:85201548577
T3 - CPE-POWERENG 2024 - 18th International Conference on Compatibility, Power Electronics and Power Engineering, Proceedings
BT - CPE-POWERENG 2024 - 18th International Conference on Compatibility, Power Electronics and Power Engineering, Proceedings
A2 - Detka, Kalina
A2 - Gorecki, Krzysztof
A2 - Gorecki, Pawel
PB - Institute of Electrical and Electronics Engineers
T2 - 18th IEEE International Conference on Compatibility, Power Electronics and Power Engineering, CPE-POWERENG 2024
Y2 - 24 June 2024 through 26 June 2024
ER -