TY - GEN
T1 - MirrorNPUF
T2 - 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
AU - Shifman, Yizhak
AU - Fish, Alexander
AU - Shor, Joseph
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022/1/1
Y1 - 2022/1/1
N2 - PUF circuits utilize multiple identical bit-cells to generate their unique keys. Thus, the Si area of each bit has a profound impact on the circuit. A method for extraction of multiple independent bits from single PUF cells is proposed. This method utilizes PUF preselection 'tilt' tests to obtain a new, uncorrelated, entropy source. During tilt tests, intentional controllable mismatch is introduced to the PUF cells, and their stability is concluded. The test could be revisited as a method to measure the internal mismatch size, by finding the tilt size required to flip the test result from 'pass' to 'fail'. As the mismatch size is random and uncorrelated, it could be used to extract multiple additional PUF bits, as well as to find the unstable bit-cells relative to each new PUF bit. A Si implementation, which relies on the capacitive tilt PUF, in TSMC 65nm, is presented, with two additional bits. This demonstrates the applicability of the scheme for multiple new bits. Measured results of the second new bit show BER of 4E-4, zero additional cell area and excellent uniqueness and randomness.
AB - PUF circuits utilize multiple identical bit-cells to generate their unique keys. Thus, the Si area of each bit has a profound impact on the circuit. A method for extraction of multiple independent bits from single PUF cells is proposed. This method utilizes PUF preselection 'tilt' tests to obtain a new, uncorrelated, entropy source. During tilt tests, intentional controllable mismatch is introduced to the PUF cells, and their stability is concluded. The test could be revisited as a method to measure the internal mismatch size, by finding the tilt size required to flip the test result from 'pass' to 'fail'. As the mismatch size is random and uncorrelated, it could be used to extract multiple additional PUF bits, as well as to find the unstable bit-cells relative to each new PUF bit. A Si implementation, which relies on the capacitive tilt PUF, in TSMC 65nm, is presented, with two additional bits. This demonstrates the applicability of the scheme for multiple new bits. Measured results of the second new bit show BER of 4E-4, zero additional cell area and excellent uniqueness and randomness.
KW - Mirror PUF
KW - preselection
KW - security
KW - tilt test
UR - http://www.scopus.com/inward/record.url?scp=85131703127&partnerID=8YFLogxK
U2 - 10.1109/ISCAS48785.2022.9937229
DO - 10.1109/ISCAS48785.2022.9937229
M3 - Conference contribution
AN - SCOPUS:85131703127
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2418
EP - 2422
BT - IEEE International Symposium on Circuits and Systems, ISCAS 2022
PB - Institute of Electrical and Electronics Engineers
Y2 - 27 May 2022 through 1 June 2022
ER -