TY - GEN
T1 - Mitigating the impact of faults in unreliable memories for error-resilient applications
AU - Ganapathy, Shrikanth
AU - Karakonstantis, Georgios
AU - Teman, Adam
AU - Burg, Andreas
N1 - Publisher Copyright:
© 2015 ACM.
PY - 2015/7/24
Y1 - 2015/7/24
N2 - Inherently error-resilient applications in areas such as signal processing, machine learning and data analytics provide opportunities for relaxing reliability requirements, and thereby reducing the overhead incurred by conventional error correction schemes. In this paper, we exploit the tolerable imprecision of such applications by designing an energy-efficient fault-mitigation scheme for unreliable data memories to meet target yield. The proposed approach uses a bit-shuffling mechanism to isolate faults into bit locations with lower significance. This skews the bit-error distribution towards the low order bits, substantially limiting the output error magnitude. By controlling the granularity of the shuffling, the proposed technique enables trading-off quality for power, area, and timing overhead. Compared to error-correction codes, this can reduce the overhead by as much as 83% in read power, 77% in read access time, and 89% in area, when applied to various data mining applications in 28nm process technology.
AB - Inherently error-resilient applications in areas such as signal processing, machine learning and data analytics provide opportunities for relaxing reliability requirements, and thereby reducing the overhead incurred by conventional error correction schemes. In this paper, we exploit the tolerable imprecision of such applications by designing an energy-efficient fault-mitigation scheme for unreliable data memories to meet target yield. The proposed approach uses a bit-shuffling mechanism to isolate faults into bit locations with lower significance. This skews the bit-error distribution towards the low order bits, substantially limiting the output error magnitude. By controlling the granularity of the shuffling, the proposed technique enables trading-off quality for power, area, and timing overhead. Compared to error-correction codes, this can reduce the overhead by as much as 83% in read power, 77% in read access time, and 89% in area, when applied to various data mining applications in 28nm process technology.
KW - Approximate Computing
KW - Bit-shuffling
KW - Error Correction
KW - Error-resilient Applications
KW - Priority-ECC
KW - Significance-driven computing
KW - Unreliable Memory
UR - http://www.scopus.com/inward/record.url?scp=84944128116&partnerID=8YFLogxK
U2 - 10.1145/2744769.2744871
DO - 10.1145/2744769.2744871
M3 - Conference contribution
AN - SCOPUS:84944128116
T3 - Proceedings - Design Automation Conference
BT - 2015 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
PB - Institute of Electrical and Electronics Engineers
T2 - 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
Y2 - 8 June 2015 through 12 June 2015
ER -
