On hyperbolic laws of capacitor discharge through self-timed digital loads

A new model to predict the dynamic behavior of a self-timed autonomous digital system powered by a capacitor is derived. The model demonstrates the hyperbolic shape of the discharging process on the capacitor. It allows a symbolic analysis of the discharging process for complex digital loads comprised of series (stack) and parallel configurations of digital circuits. For example, for a stack configuration, important non-trivial relationships between the hyperbolic discharging rates have been derived based on the knowledge of the velocity saturation index (alpha) of the semiconductor devices used in the digital part. For a realistic (modern complementary metal oxide semiconductor (CMOS) devices) value of alpha=1.5, the discharging process for a stack of two identical circuits proceeds nearly three times slower than that of any of the stand-alone circuits. This shows a potential way of extending the lifetime of the energy sources by means of stacking self-timed circuits. Although the analysis is based on configurations consisting of ring oscillators in CMOS technology, the analysis method can be extended to other types of self-timed systems and other semiconductor technologies in which the instantaneous switching activity of the digital load is determined by the instantaneous voltage levels provided by the capacitive power transfer mechanism. The analytical derivations have been validated by simulations and experiments carried out with real hardware.