On testing cache-coherent shared memories

Sequential consistency is the most-widely used correctness condition for multiprocessor memory systems. High-performance shared memory multiprocessors such as the Kendall Square KSR1, the Stanford DASH, and the MIT Alewife employ a variety of techniques to improve memory system performance while providing sequential consistency. Primary among them is the use of caches at each processor, kept coherent by protocols implemented in hardware. We study the problem of testing shared memory multiprocessors to determine if they are indeed providing a sequentially consistent memory. We present a series of results for testing an execution of a shared memory under scenarios that exploit the cache-coherence protocol. In addition to reads and writes to the shared memory, we consider the more powerful read-modify-write, load-reserved, and store-conditional operations available in many cache- coherent multiprocessors. Finally, we consider linearizability, another well-known correctness condition for shared memories. Linearizability imposes additional restrictions on the shared memory, beyond that of sequential consistency; we show that these restrictions are useful in testing such memories.