On the Minimum DC Link Capacitance in Practical PFC Rectifiers Considering THD Requirements and Load Transients

Pavel Strajnikov; Alon Kuperman

doi:10.1109/TIE.2021.3118385

On the Minimum DC Link Capacitance in Practical PFC Rectifiers Considering THD Requirements and Load Transients

Pavel Strajnikov, Alon Kuperman

Department of Electrical & Computer Engineering

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

The article presents the analytical derivation of the minimum dc link capacitance in single-phase front ends with active power factor correction (PFC) without hold-up time requirements. Such systems typically employ boost-type rectifiers; operate under restricted total harmonic distortion (THD) of the grid-side current. Moreover, PFC rectifiers must be capable of tolerating step-like zero-to-rated load power variations. It is well known that these two constraints contradict each other, posing nontrivial design challenges. The revealed value of minimum capacitance is expressed by an explicit function of grid voltage and frequency, converter rated power, dc link voltage reference, and grid current THD and voltage loop phase margin set points. Experimental results validate the proposed methodology, closely matching corresponding analytical predictions.

Original language	English
Pages (from-to)	11067-11075
Number of pages	9
Journal	IEEE Transactions on Industrial Electronics
Volume	69
Issue number	11
DOIs	https://doi.org/10.1109/TIE.2021.3118385
State	Published - 1 Nov 2022

Keywords

DC link capacitance
power factor correction (PFC)
total harmonic distortion (THD)
voltage control

ASJC Scopus subject areas

Control and Systems Engineering
Electrical and Electronic Engineering

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10.1109/TIE.2021.3118385

Cite this

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title = "On the Minimum DC Link Capacitance in Practical PFC Rectifiers Considering THD Requirements and Load Transients",

abstract = "The article presents the analytical derivation of the minimum dc link capacitance in single-phase front ends with active power factor correction (PFC) without hold-up time requirements. Such systems typically employ boost-type rectifiers; operate under restricted total harmonic distortion (THD) of the grid-side current. Moreover, PFC rectifiers must be capable of tolerating step-like zero-to-rated load power variations. It is well known that these two constraints contradict each other, posing nontrivial design challenges. The revealed value of minimum capacitance is expressed by an explicit function of grid voltage and frequency, converter rated power, dc link voltage reference, and grid current THD and voltage loop phase margin set points. Experimental results validate the proposed methodology, closely matching corresponding analytical predictions.",

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AB - The article presents the analytical derivation of the minimum dc link capacitance in single-phase front ends with active power factor correction (PFC) without hold-up time requirements. Such systems typically employ boost-type rectifiers; operate under restricted total harmonic distortion (THD) of the grid-side current. Moreover, PFC rectifiers must be capable of tolerating step-like zero-to-rated load power variations. It is well known that these two constraints contradict each other, posing nontrivial design challenges. The revealed value of minimum capacitance is expressed by an explicit function of grid voltage and frequency, converter rated power, dc link voltage reference, and grid current THD and voltage loop phase margin set points. Experimental results validate the proposed methodology, closely matching corresponding analytical predictions.

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On the Minimum DC Link Capacitance in Practical PFC Rectifiers Considering THD Requirements and Load Transients

Abstract

Keywords

ASJC Scopus subject areas

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