Abstract
As the current "Internet of Things" trend continues to grow, SoC vendors seek robust integration of wireless RF technologies into the SoC. Wireless interfaces are influenced to a great extent by digital noise, which can couple onto the RF signals. This paper presents a reliable methodology for analyzing the noise coupling mechanism in an IC package and presents ways to minimize that noise once it is found to be out of spec. The flow uses 3D field solver, circuit simulator and mathematical calculations. Successful noise coupling simulations reduce die and package manufacturing iterations and minimize lab validation time.
| Original language | English |
|---|---|
| State | Published - 1 Jan 2015 |
| Externally published | Yes |
| Event | DesignCon 2015 - Santa Clara, United States Duration: 27 Jan 2015 → 30 Jan 2015 |
Conference
| Conference | DesignCon 2015 |
|---|---|
| Country/Territory | United States |
| City | Santa Clara |
| Period | 27/01/15 → 30/01/15 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering