Phase-Locked Loop based frequency adder

Research output: Contribution to journalArticlepeer-review


The Phase-Locked Loop (PLL) frequency adder is based on the fractional N technique which is successfully applied in the frequency synthesis field. This method may be used to add two frequencies /tf1 and /tf2, i.e., to give a one frequency equal to /tf1 + /tf2. The only a priori information needed is to know that /tf1>/tf2 and that /tf1//tf2 is a rational number. The proposed method may be effectively implemented by inexpensive digital logic or on a microprocessor when the input frequencies are not too high. This method may be easily extended to frequency subtraction.

Original languageEnglish
Pages (from-to)245-252
Number of pages8
JournalSignal Processing
Issue number3
StatePublished - 1 Jan 1986


  • PLL
  • frequency adder


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