Physically Aware Affinity-Driven Multiplier Implementation

Keyphrases

• Dot Product 100%
• High Affinity 25%
• Tree-based 25%
• Commercially Available 25%
• Logic Gates 25%
• High Performance 25%
• Performance Improvement 25%
• Gate Level 25%
• 65nm CMOS 25%
• Power Reduction 25%
• Low Area 25%
• Low Performance 25%
• Integrated Circuits 25%
• Compression Algorithms 25%
• Gate-level Netlist 25%
• Place-and-route 25%
• Level Structure 25%
• Performance Optimization 25%
• Physical Implementation 25%
• Post-layout 25%
• Macro-based 25%
• Standard Cell Library 25%
• Product Approach 25%
• Clustered Dot 25%
• Routing Congestion 25%
• CMOS Standard Cell 25%

Computer Science

• Dot Product Algorithm 100%