TY - GEN
T1 - Platform independent test access port architecture
AU - Margulis, Arie
AU - Akselrod, Dimitry
AU - Wood, Tim
AU - Metsis, Sophocles
PY - 2008/12/1
Y1 - 2008/12/1
N2 - In this work, we present and analyze a generic Test Access Port (TAP) architecture capable of being re-used without any modifications in various system-on-chip (SoC) ICs as well as a "Modular Jtag" multi-TAP architecture that allows embedded IPs to control their boundary-scan segments and be IEEE 1149.1 compliant.
AB - In this work, we present and analyze a generic Test Access Port (TAP) architecture capable of being re-used without any modifications in various system-on-chip (SoC) ICs as well as a "Modular Jtag" multi-TAP architecture that allows embedded IPs to control their boundary-scan segments and be IEEE 1149.1 compliant.
UR - http://www.scopus.com/inward/record.url?scp=67249084218&partnerID=8YFLogxK
U2 - 10.1109/TEST.2008.4700687
DO - 10.1109/TEST.2008.4700687
M3 - Conference contribution
AN - SCOPUS:67249084218
SN - 9781424424030
T3 - Proceedings - International Test Conference
BT - Proceedings - International Test Conference 2008, ITC 2008
T2 - International Test Conference 2008, ITC 2008
Y2 - 28 October 2008 through 30 October 2008
ER -