Platform independent test access port architecture

Arie Margulis, Dimitry Akselrod, Tim Wood, Sophocles Metsis

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this work, we present and analyze a generic Test Access Port (TAP) architecture capable of being re-used without any modifications in various system-on-chip (SoC) ICs as well as a "Modular Jtag" multi-TAP architecture that allows embedded IPs to control their boundary-scan segments and be IEEE 1149.1 compliant.

Original languageEnglish
Title of host publicationProceedings - International Test Conference 2008, ITC 2008
DOIs
StatePublished - 1 Dec 2008
Externally publishedYes
EventInternational Test Conference 2008, ITC 2008 - Santa Clara, CA, United States
Duration: 28 Oct 200830 Oct 2008

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Conference

ConferenceInternational Test Conference 2008, ITC 2008
Country/TerritoryUnited States
CitySanta Clara, CA
Period28/10/0830/10/08

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

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