TY - GEN
T1 - Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications
AU - Giterman, Robert
AU - Wicentowski, Maoz
AU - Chertkow, Oron
AU - Sever, Ilan
AU - Kehati, Ishai
AU - Weizman, Yoav
AU - Keren, Osnat
AU - Fish, Alexander
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/9/1
Y1 - 2019/9/1
N2 - Power analysis attacks are an effective tool to extract sensitive information using side-channel analysis,forming a serious threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with conventional 6T SRAM macrocells often dominate the area and power of these SoCs. In this paper,for the first time,we use silicon measurements to prove that conventional SRAM arrays leak valuable information and that their data can be extracted using power analysis attacks. In order to provide a power analysis resilient embedded memory and adhere to the area constraints of modern SoCs,we implement a low-cost impedance randomization unit,which is integrated into the periphery of a conventional 6T SRAM macro. Preliminary silicon measurements of a 55 nm test-chip implementing the proposed memory array demonstrate a significant information leakage reduction at a low-cost 1% area overhead and no speed and power penalties compared to a conventional SRAM design.
AB - Power analysis attacks are an effective tool to extract sensitive information using side-channel analysis,forming a serious threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with conventional 6T SRAM macrocells often dominate the area and power of these SoCs. In this paper,for the first time,we use silicon measurements to prove that conventional SRAM arrays leak valuable information and that their data can be extracted using power analysis attacks. In order to provide a power analysis resilient embedded memory and adhere to the area constraints of modern SoCs,we implement a low-cost impedance randomization unit,which is integrated into the periphery of a conventional 6T SRAM macro. Preliminary silicon measurements of a 55 nm test-chip implementing the proposed memory array demonstrate a significant information leakage reduction at a low-cost 1% area overhead and no speed and power penalties compared to a conventional SRAM design.
UR - http://www.scopus.com/inward/record.url?scp=85075930232&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC.2019.8902622
DO - 10.1109/ESSCIRC.2019.8902622
M3 - Conference contribution
AN - SCOPUS:85075930232
T3 - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
SP - 69
EP - 72
BT - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
PB - Institute of Electrical and Electronics Engineers
T2 - 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019
Y2 - 23 September 2019 through 26 September 2019
ER -