Power-management architecture of the intel microarchitecture code-named Sandy Bridge

Efraim Rotem; Alon Naveh; Avinash Ananthakrishnan; Eliezer Weissmann; Doron Rajwan

doi:10.1109/MM.2012.12

Power-management architecture of the intel microarchitecture code-named Sandy Bridge

Efraim Rotem
, Alon Naveh
, Avinash Ananthakrishnan
, Eliezer Weissmann
, Doron Rajwan

Research output: Contribution to journal › Article › peer-review

402 Scopus citations

Abstract

Modern microprocessors are evolving into system-on-a-chip designs with high integration levels, catering to ever-shrinking form factors. Portability without compromising performance is a driving market need. An architectural approach that's adaptive to and cognizant of workload behavior and platform physical constraints is indispensable to meeting these performance and efficiency goals. This article describes power-management innovations introduced on Intel's Sandy Bridge microprocessor.

Original language	English
Pages (from-to)	20-27
Number of pages	8
Journal	IEEE Micro
Volume	32
Issue number	2
DOIs	https://doi.org/10.1109/MM.2012.12
State	Published - 1 Mar 2012
Externally published	Yes

Keywords

Sandy Bridge
Turbo Boost
energy management
power management

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MM.2012.12

Cite this

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AU - Rajwan, Doron

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Power-management architecture of the intel microarchitecture code-named Sandy Bridge

Abstract

Keywords

ASJC Scopus subject areas

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