Preliminary analysis of RISC architectures performance

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

Analysing architecture performance is a step of utmost importance and interest in the process of computer architecture design. The paper deals particularly with special architectures of the Reduced Instruction Set Computer Space (RISCS) in order to obtain a preliminary evaluation of RISC's architectures performance and the approach to an optimal instruction set for an effective High Level Language Computer (HLLC). The new modular microcomputer consisting of instruction groups modules called MODHEL that has already been proposed has facilitated the investigation of the performance of a set of computers allocated within the RISCS. A comparative study of the dynamic instruction mix of four benchmark programs is performed with respect to the VAX 11/780, RISCI (Berkeley) and five versions of MODHEL. Preliminary results indicate that there is a strong chance that RISC-type computers could be designed to function as efficient low-cost systems.

Original languageEnglish
Pages (from-to)133-137
Number of pages5
JournalMicroprocessing and Microprogramming
Volume14
Issue number3-4
DOIs
StatePublished - 1 Jan 1984

Keywords

  • Computer Architecture Performance Evaluation
  • Computer Performance
  • Instruction Modularity
  • Reduced Instructions Set Computers
  • Special Computer Architecture

Fingerprint

Dive into the research topics of 'Preliminary analysis of RISC architectures performance'. Together they form a unique fingerprint.

Cite this