Process variation-aware datapath employing dual mode logic

Netanel Shavit, Inbal Stanger, Ramiro Taco, Alexander Fish

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Dual Mode Logic (DML), which was recently introduced by our group, offers the possibility to operate digital gates either in the static mode to save energy, or in the dynamic mode to increase speed albeit with a higher delay or energy consumption, respectively. We showed that on-the-fly switching of critical paths between the static and dynamic modes enabled system self-adaptation to computational needs achieving both high speed and low energy consumption. In this paper, for the first time we show that the mixed mode operation of a DML based datapath can efficiently reduce design sensitivity to process variations at near threshold voltages. Specifically, the number of gates operating in the dynamic mode (when the datapath is switched to the high-performance mode) is selected as a function of the process corner. The number of dynamically operated gates can be adjusted during the post-silicon phase or at run-time with an architectural level solution. In a basic proof of concept, simulations of a chain of 20 NAND/NOR gates demonstrated that process variations were successfully alleviated by utilizing an optimal configuration of the chain. The DML design can meet CMOS TT performance requirements in the SS corner and save energy by 18% in the FF corner. A 64-bit ripple carry adder (RCA) confirmed the advantages of DML over CMOS for different optimization points.

Original languageEnglish
Title of host publication2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538676264
DOIs
StatePublished - 11 Feb 2019
Externally publishedYes
Event2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 - Burlingame, United States
Duration: 15 Oct 201818 Oct 2018

Publication series

Name2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018

Conference

Conference2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
Country/TerritoryUnited States
CityBurlingame
Period15/10/1818/10/18

Keywords

  • Dual Mode Logic (DML)
  • Dynamic logic
  • Process variation
  • Static cmos
  • Ultra-low voltage

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