TY - JOUR
T1 - Providing performance guarantees in multipass network processors
AU - Keslassy, Isaac
AU - Kogan, Kirill
AU - Scalosub, Gabriel
AU - Segal, Michael
N1 - Funding Information:
Manuscript received June 24, 2011; revised January 05, 2012; accepted January 29, 2012; approved by IEEE/ACM TRANSACTIONS ON NETWORKING Editor P. Crowley. Date of publication February 23, 2012; date of current version December 13, 2012. This work was supported in part by the US Air Force European Office of Aerospace Research and Development under Grant FA8655-09-1-3016, Deutsche Telecom, the European project FLAVIA, the Israeli Ministry of Industry, Trade and Labor (consortium CORNET), and the European Research Council under Starting Grant No. 210389. A preliminary version of this paper was presented at the IEEE International Conference on Computer Communications (INFOCOM), Shanghai, China, April 10–15, 2011.
Funding Information:
Dr. Keslassy is an Associate Editor for the IEEE/ACM TRANSACTIONS ON NETWORKING. He is the recipient of the European Research Council Starting Grant, the Yigal Alon Fellowship, and the ATS-WD Career Development Chair.
Publisher Copyright:
© 2012 IEEE.
PY - 2012/12/1
Y1 - 2012/12/1
N2 - Current network processors (NPs) increasingly deal with packets with heterogeneous processing times. In such an environment, packets that require many processing cycles delay low-latency traffic because the common approach in today's NPs is to employ run-to-completion processing. These difficulties have led to the emergence of theMultipass NP architecture, where after a processing cycle ends, all processed packets are recycled into the buffer and recompete for processing resources. In this paper, we provide a model that captures many of the characteristics of this architecture, and we consider several scheduling and buffer management algorithms that are specially designed to optimize the performance of multipass network processors. In particular, we provide analytical guarantees for the throughput performance of our algorithms. We further conduct a comprehensive simulation study, which validates our results.
AB - Current network processors (NPs) increasingly deal with packets with heterogeneous processing times. In such an environment, packets that require many processing cycles delay low-latency traffic because the common approach in today's NPs is to employ run-to-completion processing. These difficulties have led to the emergence of theMultipass NP architecture, where after a processing cycle ends, all processed packets are recycled into the buffer and recompete for processing resources. In this paper, we provide a model that captures many of the characteristics of this architecture, and we consider several scheduling and buffer management algorithms that are specially designed to optimize the performance of multipass network processors. In particular, we provide analytical guarantees for the throughput performance of our algorithms. We further conduct a comprehensive simulation study, which validates our results.
KW - Buffer management algorithms
KW - Competitive analysis
KW - Network processors (NPs)
KW - Scheduling
UR - http://www.scopus.com/inward/record.url?scp=85042784227&partnerID=8YFLogxK
U2 - 10.1109/TNET.2012.2186979
DO - 10.1109/TNET.2012.2186979
M3 - Article
AN - SCOPUS:85042784227
SN - 1063-6692
VL - 20
SP - 1895
EP - 1909
JO - IEEE/ACM Transactions on Networking
JF - IEEE/ACM Transactions on Networking
IS - 6
ER -