TY - GEN
T1 - PURR
T2 - 15th ACM International Conference on Emerging Networking Experiments and Technologies, CoNEXT 2019
AU - Chiesa, Marco
AU - Sedar, Roshan
AU - Antichi, Gianni
AU - Borokhovich, Michael
AU - Kamisiński, Andrzej
AU - Nikolaidis, Georgios
AU - Schmid, Stefan
N1 - Publisher Copyright:
© 2019 ACM.
PY - 2019/12/3
Y1 - 2019/12/3
N2 - Highly dependable communication networks usually rely on some kind of Fast Re-Route (FRR) mechanism which allows to quickly re-route traffic upon failures, entirely in the data plane. This paper studies the design of FRR mechanisms for emerging reconfigurable switches. Our main contribution is an FRR primitive for programmable data planes, PURR, which provides low failover latency and high switch throughput, by avoiding packet recirculation. PURR tolerates multiple concurrent failures and comes with minimal memory requirements, ensuring compact forwarding tables, by unveiling an intriguing connection to classic "string theory" (i.e., stringology), and in particular, the shortest common supersequence problem. PURR is well-suited for high-speed match-action forwarding architectures (e.g., PISA) and supports the implementation of arbitrary network-wide FRR mechanisms. Our simulations and prototype implementation (on an FPGA and Tofino) show that PURR improves TCAM memory occupancy by a factor of 1.5x - 10.8x compared to a naïve encoding when implementing state-of-the-art FRR mechanisms. PURR also improves the latency and throughput of datacenter traffic up to a factor of 2.8x - 5.5x and 1.2x - 2x, respectively, compared to approaches based on recirculating packets.
AB - Highly dependable communication networks usually rely on some kind of Fast Re-Route (FRR) mechanism which allows to quickly re-route traffic upon failures, entirely in the data plane. This paper studies the design of FRR mechanisms for emerging reconfigurable switches. Our main contribution is an FRR primitive for programmable data planes, PURR, which provides low failover latency and high switch throughput, by avoiding packet recirculation. PURR tolerates multiple concurrent failures and comes with minimal memory requirements, ensuring compact forwarding tables, by unveiling an intriguing connection to classic "string theory" (i.e., stringology), and in particular, the shortest common supersequence problem. PURR is well-suited for high-speed match-action forwarding architectures (e.g., PISA) and supports the implementation of arbitrary network-wide FRR mechanisms. Our simulations and prototype implementation (on an FPGA and Tofino) show that PURR improves TCAM memory occupancy by a factor of 1.5x - 10.8x compared to a naïve encoding when implementing state-of-the-art FRR mechanisms. PURR also improves the latency and throughput of datacenter traffic up to a factor of 2.8x - 5.5x and 1.2x - 2x, respectively, compared to approaches based on recirculating packets.
KW - Fast failover
KW - Fast reroute
KW - Network robustness
KW - Programmable networks
KW - Shortest common supersequence
UR - https://www.scopus.com/pages/publications/85077239904
U2 - 10.1145/3359989.3365410
DO - 10.1145/3359989.3365410
M3 - Conference contribution
AN - SCOPUS:85077239904
T3 - CoNEXT 2019 - Proceedings of the 15th International Conference on Emerging Networking Experiments and Technologies
SP - 1
EP - 14
BT - CoNEXT 2019 - Proceedings of the 15th International Conference on Emerging Networking Experiments and Technologies
PB - Association for Computing Machinery, Inc
Y2 - 9 December 2019 through 12 December 2019
ER -