Redundant Linear Coding for accelerating counting and comparison operations

I. Elhanany; O. Arazi

doi:10.1109/ISCAS.2000.857432

Redundant Linear Coding for accelerating counting and comparison operations

I. Elhanany
, O. Arazi

Department of Electrical & Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

Abstract

A novel binary number system, called Redundant Linear Coding (RLC), is presented. By eliminating the need for carry handling, a feasible tradeoff between speed and area yields short computation time for up/down counting and comparison operations. The scheme can efficiently be applied to a wide range of high-speed digital applications.

Original language	English
Pages (from-to)	V-333-V-336
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	5
DOIs	https://doi.org/10.1109/ISCAS.2000.857432
State	Published - 1 Jan 2000
Event	Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland Duration: 28 May 2000 → 31 May 2000

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ISCAS.2000.857432

Cite this

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title = "Redundant Linear Coding for accelerating counting and comparison operations",

abstract = "A novel binary number system, called Redundant Linear Coding (RLC), is presented. By eliminating the need for carry handling, a feasible tradeoff between speed and area yields short computation time for up/down counting and comparison operations. The scheme can efficiently be applied to a wide range of high-speed digital applications.",

author = "I. Elhanany and O. Arazi",

year = "2000",

month = jan,

day = "1",

doi = "10.1109/ISCAS.2000.857432",

language = "English",

volume = "5",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers",

note = "Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 ; Conference date: 28-05-2000 Through 31-05-2000",

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TY - JOUR

T1 - Redundant Linear Coding for accelerating counting and comparison operations

AU - Elhanany, I.

AU - Arazi, O.

PY - 2000/1/1

Y1 - 2000/1/1

N2 - A novel binary number system, called Redundant Linear Coding (RLC), is presented. By eliminating the need for carry handling, a feasible tradeoff between speed and area yields short computation time for up/down counting and comparison operations. The scheme can efficiently be applied to a wide range of high-speed digital applications.

AB - A novel binary number system, called Redundant Linear Coding (RLC), is presented. By eliminating the need for carry handling, a feasible tradeoff between speed and area yields short computation time for up/down counting and comparison operations. The scheme can efficiently be applied to a wide range of high-speed digital applications.

UR - https://www.scopus.com/pages/publications/0033721866

U2 - 10.1109/ISCAS.2000.857432

DO - 10.1109/ISCAS.2000.857432

M3 - Conference article

AN - SCOPUS:0033721866

SN - 0271-4310

VL - 5

SP - V-333-V-336

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000

Y2 - 28 May 2000 through 31 May 2000

ER -

Redundant Linear Coding for accelerating counting and comparison operations

Abstract

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