TY - GEN

T1 - Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications

AU - Zabib, David Zooker

AU - Levi, Itamar

AU - Fish, Alexander

AU - Keren, Osnat

N1 - Publisher Copyright:
© 2017 IEEE.

PY - 2017/7/2

Y1 - 2017/7/2

N2 - Hardware implementations of cryptographic algorithms may leak information through numerous side channels, which can be used to reveal the secret cryptographic keys, and therefore compromise the security of the algorithm. Power Analysis Attacks (PAAs) [1] exploit the information leakage from the device's power consumption (typically measured on the supply and/or ground pins). Digital circuits consume dynamic switching energy when data propagate through the logic in each new calculation (e.g. new clock cycle). The average power dissipation of a design can be expressed by: Ptot(t) = α · (Pd(t) + Ppvt(t)) (1) where α is the activity factor (the probability that the gate will switch) and depends on the probability distribution of the inputs to the combinatorial logic. This induces a linear relationship between the power and the processed data [2]. Pd is the deterministic power dissipated by the switching of the gate, including any parasitic and intrinsic capacitances, and hence can be evaluated prior to manufacturing. Ppvt is the change in expected power consumption due to nondeterministic parameters such as process variations, mismatch, temperature, etc. In this manuscript, we describe the design of logic gates that induce data-independent (constant) α and Pd.

AB - Hardware implementations of cryptographic algorithms may leak information through numerous side channels, which can be used to reveal the secret cryptographic keys, and therefore compromise the security of the algorithm. Power Analysis Attacks (PAAs) [1] exploit the information leakage from the device's power consumption (typically measured on the supply and/or ground pins). Digital circuits consume dynamic switching energy when data propagate through the logic in each new calculation (e.g. new clock cycle). The average power dissipation of a design can be expressed by: Ptot(t) = α · (Pd(t) + Ppvt(t)) (1) where α is the activity factor (the probability that the gate will switch) and depends on the probability distribution of the inputs to the combinatorial logic. This induces a linear relationship between the power and the processed data [2]. Pd is the deterministic power dissipated by the switching of the gate, including any parasitic and intrinsic capacitances, and hence can be evaluated prior to manufacturing. Ppvt is the change in expected power consumption due to nondeterministic parameters such as process variations, mismatch, temperature, etc. In this manuscript, we describe the design of logic gates that induce data-independent (constant) α and Pd.

UR - http://www.scopus.com/inward/record.url?scp=85047766509&partnerID=8YFLogxK

U2 - 10.1109/S3S.2017.8309254

DO - 10.1109/S3S.2017.8309254

M3 - Conference contribution

AN - SCOPUS:85047766509

T3 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

SP - 1

EP - 2

BT - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

PB - Institute of Electrical and Electronics Engineers

T2 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

Y2 - 16 October 2017 through 18 October 2017

ER -