Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications

David Zooker Zabib, Itamar Levi, Alexander Fish, Osnat Keren

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Hardware implementations of cryptographic algorithms may leak information through numerous side channels, which can be used to reveal the secret cryptographic keys, and therefore compromise the security of the algorithm. Power Analysis Attacks (PAAs) [1] exploit the information leakage from the device's power consumption (typically measured on the supply and/or ground pins). Digital circuits consume dynamic switching energy when data propagate through the logic in each new calculation (e.g. new clock cycle). The average power dissipation of a design can be expressed by: Ptot(t) = α · (Pd(t) + Ppvt(t)) (1) where α is the activity factor (the probability that the gate will switch) and depends on the probability distribution of the inputs to the combinatorial logic. This induces a linear relationship between the power and the processed data [2]. Pd is the deterministic power dissipated by the switching of the gate, including any parasitic and intrinsic capacitances, and hence can be evaluated prior to manufacturing. Ppvt is the change in expected power consumption due to nondeterministic parameters such as process variations, mismatch, temperature, etc. In this manuscript, we describe the design of logic gates that induce data-independent (constant) α and Pd.

Original languageEnglish
Title of host publication2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-2
Number of pages2
ISBN (Electronic)9781538637654
DOIs
StatePublished - 7 Mar 2018
Externally publishedYes
Event2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 - Burlingame, United States
Duration: 16 Oct 201718 Oct 2017

Publication series

Name2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Volume2018-March

Conference

Conference2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Country/TerritoryUnited States
CityBurlingame
Period16/10/1718/10/17

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