Selective state retention power gating based on gate-level analysis

Shlomo Greenberg, Joseph Rabinowicz, Ron Tsechanski, Eugene Paperno

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

This work presents a novel approach based on gate-level analysis for implementing Selective State Retention Power Gating (SSRPG). A selective SRPG approach mitigates the area and power overhead of the conventional SRPG technique. However, only very few papers suggesting a selective SPRG approach were published. The proposed SSRPG technique employs a formal analysis and, therefore, does not require exhaustive simulations. To implement the new approach, an automatic algorithm, which is performed on a gate-level netlist, has been developed. This algorithm enables the extraction of a subset of flip-flops that is sufficient for a proper state retention power gating. Unique selective SRPG criteria have been defined to support the proposed algorithm. These criteria are used to reduce the total amount of the required retention cells. To the best of our knowledge, this is the first robust SSRPG approach using gate-level analysis for selecting a reduced sub set of FFs that require retention. The proposed approach has been applied to a practical design with about 3300 FFs. The experimental results show 78% reduction of the retention SPRG cell area overhead, compared to the common SRPG approach.

Original languageEnglish
Article number6668988
Pages (from-to)1095-1104
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume61
Issue number4
DOIs
StatePublished - 1 Jan 2014

Keywords

  • Low power design
  • power gating
  • selective state retention power gating
  • state retention power gating

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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