SEU Hardening: Incorporating an Extreme Low Power Bitcell Design (SHIELD)

Ariel Pescovsky, Oron Chertkow, Lior Atias, Alexander Fish

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. In this paper, a novel 'SEU Hardening Incorporating Extreme Low Power Bitcell Design' (SHIELD) is proposed to attend these two major concerns simultaneously. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC when operated at a scaled 700mV supply voltage utilizing a 65nm process. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions.

Original languageEnglish
Title of host publication2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479974382
DOIs
StatePublished - 30 Jan 2014
Externally publishedYes
Event2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014 - Millbrae, United States
Duration: 6 Oct 20149 Oct 2014

Publication series

Name2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014

Conference

Conference2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
Country/TerritoryUnited States
CityMillbrae
Period6/10/149/10/14

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