@article{08166d3e06a24ca09c5c07aef2f437b2,
title = "Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths",
abstract = "This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of-concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from -40 °C to 125 °C confirm the effectiveness of this approach to compensate for severe process, voltage and temperature (PVT) variations.",
keywords = "Dual mode logic (DML), PVT variation tolerance, adaptive circuits",
author = "Inbal Stanger and Netanel Shavit and Ramiro Taco and Marco Lanuzza and Alexander Fish",
note = "Funding Information: Manuscript received June 17, 2020; revised July 21, 2020; accepted July 27, 2020. Date of publication July 31, 2020; date of current version September 3, 2020. This work was supported in part by the Israel Innovation Authority in the Frame of the GenPro Consortium; and in part by the Israel Ministry of Science and Technology and the Golda Meir Scholarship under Grant 3-14361. This brief was recommended by Associate Editor J. Yang. (Corresponding author: Inbal Stanger.) Inbal Stanger, Netanel Shavit, and Alexander Fish are with the Emerging Nanoscaled Integrated Circuits and Systems Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan 5290002, Israel (e-mail: inbal.stanger@biu.ac.il; netanel.shavit@biu.ac.il; alexander.fish@biu.ac.il). Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",
year = "2020",
month = sep,
day = "1",
doi = "10.1109/TCSII.2020.3013331",
language = "English",
volume = "67",
pages = "1639--1643",
journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",
issn = "1549-7747",
publisher = "Institute of Electrical and Electronics Engineers",
number = "9",
}