TY - GEN
T1 - Silicon-Proven Clockless Wave-Propagated Pipelining for High-Throughput, Energy-Efficient Processing
AU - Kra, Yehuda
AU - Teman, Adam
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022/1/1
Y1 - 2022/1/1
N2 - The vast majority of digital systems are designed using pipelined sequential logic, thanks to a well-known and robust implementation flow with the ability to increase throughput simply by introducing intermediate sampling stages. However, adding these registers results in significant area and power overheads. Clockless Wave-Propagated Pipelining (CWPP) is a design approach that reaches high throughputs without the need for intermediate sampling registers.
AB - The vast majority of digital systems are designed using pipelined sequential logic, thanks to a well-known and robust implementation flow with the ability to increase throughput simply by introducing intermediate sampling stages. However, adding these registers results in significant area and power overheads. Clockless Wave-Propagated Pipelining (CWPP) is a design approach that reaches high throughputs without the need for intermediate sampling registers.
UR - https://www.scopus.com/pages/publications/85142521889
U2 - 10.1109/ISCAS48785.2022.9937508
DO - 10.1109/ISCAS48785.2022.9937508
M3 - Conference contribution
AN - SCOPUS:85142521889
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1138
EP - 1139
BT - IEEE International Symposium on Circuits and Systems, ISCAS 2022
PB - Institute of Electrical and Electronics Engineers
T2 - 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
Y2 - 27 May 2022 through 1 June 2022
ER -