Single event upset mitigation in low power SRAM design

Lior Atias, Adam Teman, Alexander Fish

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

Technology advancements in recent years have led to an increase in the employment of integrated circuits in space applications. However, these applications operate in a highly radiated environment, causing a high probability of single event upsets (SEU). Continuous transistor scaling exacerbates the situation, as susceptibility to SEUs is increased in advanced process technologies. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Accordingly, maintaining data integrity in light of SEUs has become an integral aspect of memory cell design. This paper introduces recently proposed methods for mitigating SEUs, and reviews the advantages and disadvantages of leading memory radiation hardening solutions. A brief comparison of radiation hardened bitcells is provided, based on Monte Carlo simulations in a 65nm CMOS process under slightly scaled supply voltages.

Original languageEnglish
Title of host publication2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479959877
DOIs
StatePublished - 1 Jan 2014
Externally publishedYes
Event2014 28th IEEE Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014 - Eilat, Israel
Duration: 3 Dec 20145 Dec 2014

Publication series

Name2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014

Conference

Conference2014 28th IEEE Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014
Country/TerritoryIsrael
CityEilat
Period3/12/145/12/14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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