TY - GEN
T1 - Single event upset mitigation in low power SRAM design
AU - Atias, Lior
AU - Teman, Adam
AU - Fish, Alexander
N1 - Publisher Copyright:
© Copyright 2015 IEEE All rights reserved.
PY - 2014/1/1
Y1 - 2014/1/1
N2 - Technology advancements in recent years have led to an increase in the employment of integrated circuits in space applications. However, these applications operate in a highly radiated environment, causing a high probability of single event upsets (SEU). Continuous transistor scaling exacerbates the situation, as susceptibility to SEUs is increased in advanced process technologies. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Accordingly, maintaining data integrity in light of SEUs has become an integral aspect of memory cell design. This paper introduces recently proposed methods for mitigating SEUs, and reviews the advantages and disadvantages of leading memory radiation hardening solutions. A brief comparison of radiation hardened bitcells is provided, based on Monte Carlo simulations in a 65nm CMOS process under slightly scaled supply voltages.
AB - Technology advancements in recent years have led to an increase in the employment of integrated circuits in space applications. However, these applications operate in a highly radiated environment, causing a high probability of single event upsets (SEU). Continuous transistor scaling exacerbates the situation, as susceptibility to SEUs is increased in advanced process technologies. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Accordingly, maintaining data integrity in light of SEUs has become an integral aspect of memory cell design. This paper introduces recently proposed methods for mitigating SEUs, and reviews the advantages and disadvantages of leading memory radiation hardening solutions. A brief comparison of radiation hardened bitcells is provided, based on Monte Carlo simulations in a 65nm CMOS process under slightly scaled supply voltages.
UR - https://www.scopus.com/pages/publications/84941242836
U2 - 10.1109/EEEI.2014.7005796
DO - 10.1109/EEEI.2014.7005796
M3 - Conference contribution
AN - SCOPUS:84941242836
T3 - 2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014
BT - 2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014
PB - Institute of Electrical and Electronics Engineers
T2 - 2014 28th IEEE Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014
Y2 - 3 December 2014 through 5 December 2014
ER -