TY - JOUR
T1 - Single-Event Upset Tolerance Study of a Low-Voltage 13T Radiation-Hardened SRAM Bitcell
AU - Haran, Avner
AU - Keren, Eitan
AU - David, David
AU - Refaeli, Nati
AU - Giterman, Robert
AU - Assaf, Matan
AU - Atias, Lior
AU - Teman, Adam
AU - Fish, Alexander
N1 - Funding Information:
Manuscript received March 19, 2020; revised May 4, 2020 and May 31, 2020; accepted June 3, 2020. Date of publication June 15, 2020; date of current version August 14, 2020. This work was supported in part by the Israeli Ministry of Science and Technology.
Publisher Copyright:
© 1963-2012 IEEE.
PY - 2020/8/1
Y1 - 2020/8/1
N2 - The 13T static random-access memory (SRAM) cell was designed as a low-voltage single-event upset (SEU)-tolerant device for ultralow power space applications, showing full read and write functionality down to the subthreshold voltage of 300 mV. In order to assess the SEU hardness of the device experimentally, it was tested under heavy-ion beams at the Cyclotron Resource Center, Louvain-la-Neuve, Belgium. After irradiation, bit upsets from '1' to '0' were observed, whereas bit upsets from '0' to '1' were extremely rare. Since multiple upsets occurred within addresses, we assume that in addition to random ion hits on the memory cells, the reason for the high SEU rate is ions impinging on the nonhardened peripheral circuitry. Furthermore, heavy-ion experiments and Monte Carlo simulations were performed in order to clarify the upset mechanism.
AB - The 13T static random-access memory (SRAM) cell was designed as a low-voltage single-event upset (SEU)-tolerant device for ultralow power space applications, showing full read and write functionality down to the subthreshold voltage of 300 mV. In order to assess the SEU hardness of the device experimentally, it was tested under heavy-ion beams at the Cyclotron Resource Center, Louvain-la-Neuve, Belgium. After irradiation, bit upsets from '1' to '0' were observed, whereas bit upsets from '0' to '1' were extremely rare. Since multiple upsets occurred within addresses, we assume that in addition to random ion hits on the memory cells, the reason for the high SEU rate is ions impinging on the nonhardened peripheral circuitry. Furthermore, heavy-ion experiments and Monte Carlo simulations were performed in order to clarify the upset mechanism.
KW - 13T bitcell
KW - radiation hardening by design (RHBD)
KW - single-event upset (SEU)
KW - static random-access memory (SRAM)
UR - http://www.scopus.com/inward/record.url?scp=85089875637&partnerID=8YFLogxK
U2 - 10.1109/TNS.2020.3002654
DO - 10.1109/TNS.2020.3002654
M3 - Article
AN - SCOPUS:85089875637
VL - 67
SP - 1803
EP - 1812
JO - IEEE Transactions on Nuclear Science
JF - IEEE Transactions on Nuclear Science
SN - 0018-9499
IS - 8
M1 - 9117141
ER -