State space modeling for sub-threshold SRAM stability analysis

Janna Mezhibovsky, Adam Teman, Alexander Fish

Research output: Contribution to conferencePaperpeer-review

7 Scopus citations


Continuous technology scaling has made traditional Static Noise Margin metrics for stability analysis of SRAM bitcells insufficient. Today, Dynamic Noise Margin analyses and metrics are necessary for state-of-the-art bitcell design, especially under problematic low-voltage operation. In this paper, we overview the concept of state-space modeling for dynamic stability analysis, and then develop an analytical method for evaluating SRAM bitcell operation in the sub-threshold regime. An algorithm for state-space and phase-portrait plotting is proposed and shown to correctly predict subthreshold hold and write behavior of standard bitcells in a 40nm CMOS technology. Implementation of the presented technique in mathematical CAD tools provides orders of magnitude faster evaluation than using traditional brute force approaches.

Original languageEnglish
Number of pages4
StatePublished - 28 Sep 2012
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 20 May 201223 May 2012


Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/TerritoryKorea, Republic of

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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