State space modeling for sub-threshold SRAM stability analysis

Janna Mezhibovsky; Adam Teman; Alexander Fish

doi:10.1109/ISCAS.2012.6271622

State space modeling for sub-threshold SRAM stability analysis

Janna Mezhibovsky
, Adam Teman
, Alexander Fish

Department of Electrical & Computer Engineering

Research output: Contribution to conference › Paper › peer-review

7 Scopus citations

Abstract

Continuous technology scaling has made traditional Static Noise Margin metrics for stability analysis of SRAM bitcells insufficient. Today, Dynamic Noise Margin analyses and metrics are necessary for state-of-the-art bitcell design, especially under problematic low-voltage operation. In this paper, we overview the concept of state-space modeling for dynamic stability analysis, and then develop an analytical method for evaluating SRAM bitcell operation in the sub-threshold regime. An algorithm for state-space and phase-portrait plotting is proposed and shown to correctly predict subthreshold hold and write behavior of standard bitcells in a 40nm CMOS technology. Implementation of the presented technique in mathematical CAD tools provides orders of magnitude faster evaluation than using traditional brute force approaches.

Original language	English
Pages	1823-1826
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271622
State	Published - 28 Sep 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 20 May 2012 → 23 May 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	20/05/12 → 23/05/12

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ISCAS.2012.6271622

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title = "State space modeling for sub-threshold SRAM stability analysis",

abstract = "Continuous technology scaling has made traditional Static Noise Margin metrics for stability analysis of SRAM bitcells insufficient. Today, Dynamic Noise Margin analyses and metrics are necessary for state-of-the-art bitcell design, especially under problematic low-voltage operation. In this paper, we overview the concept of state-space modeling for dynamic stability analysis, and then develop an analytical method for evaluating SRAM bitcell operation in the sub-threshold regime. An algorithm for state-space and phase-portrait plotting is proposed and shown to correctly predict subthreshold hold and write behavior of standard bitcells in a 40nm CMOS technology. Implementation of the presented technique in mathematical CAD tools provides orders of magnitude faster evaluation than using traditional brute force approaches.",

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doi = "10.1109/ISCAS.2012.6271622",

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T1 - State space modeling for sub-threshold SRAM stability analysis

AU - Mezhibovsky, Janna

AU - Teman, Adam

AU - Fish, Alexander

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Y1 - 2012/9/28

N2 - Continuous technology scaling has made traditional Static Noise Margin metrics for stability analysis of SRAM bitcells insufficient. Today, Dynamic Noise Margin analyses and metrics are necessary for state-of-the-art bitcell design, especially under problematic low-voltage operation. In this paper, we overview the concept of state-space modeling for dynamic stability analysis, and then develop an analytical method for evaluating SRAM bitcell operation in the sub-threshold regime. An algorithm for state-space and phase-portrait plotting is proposed and shown to correctly predict subthreshold hold and write behavior of standard bitcells in a 40nm CMOS technology. Implementation of the presented technique in mathematical CAD tools provides orders of magnitude faster evaluation than using traditional brute force approaches.

AB - Continuous technology scaling has made traditional Static Noise Margin metrics for stability analysis of SRAM bitcells insufficient. Today, Dynamic Noise Margin analyses and metrics are necessary for state-of-the-art bitcell design, especially under problematic low-voltage operation. In this paper, we overview the concept of state-space modeling for dynamic stability analysis, and then develop an analytical method for evaluating SRAM bitcell operation in the sub-threshold regime. An algorithm for state-space and phase-portrait plotting is proposed and shown to correctly predict subthreshold hold and write behavior of standard bitcells in a 40nm CMOS technology. Implementation of the presented technique in mathematical CAD tools provides orders of magnitude faster evaluation than using traditional brute force approaches.

UR - https://www.scopus.com/pages/publications/84866631945

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DO - 10.1109/ISCAS.2012.6271622

M3 - Paper

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T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

Y2 - 20 May 2012 through 23 May 2012

ER -

State space modeling for sub-threshold SRAM stability analysis

Abstract

Conference

ASJC Scopus subject areas

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