TY - GEN
T1 - Statistical approach to NoC design
AU - Cohen, Itamar
AU - Rottenstreich, Ori
AU - Keslassy, Isaac
PY - 2008/5/28
Y1 - 2008/5/28
N2 - Chip multiprocessors (CMPs) combine increasingly many general-purpose processor cores on a single chip. These cores run several tasks with unpredictable communication needs, resulting in uncertain and often-changing traffic patterns. This unpredictability leads network-on-chip (NoC) designers to plan for the worst-case traffic patterns, and significantly over-provision link capacities. In this paper, we provide NoC designers with an alternative statistical approach. We first present the traffic-load distribution plots (T-Plots), illustrating how much capacity over-provisioning is needed to service 90%, 99%, or 100% of all traffic patterns. We prove that in the general case, plotting T-Plots is #P-complete, and therefore extremely complex. We then show how to determine the exact mean and variance of the traffic load on any edge, and use these to provide Gaussian-based models for the T-Plots, as well as guaranteed performance bounds. Finally, we use T-Plots to reduce the network power consumption by providing an efficient capacity allocation algorithm with predictable performance guarantees.
AB - Chip multiprocessors (CMPs) combine increasingly many general-purpose processor cores on a single chip. These cores run several tasks with unpredictable communication needs, resulting in uncertain and often-changing traffic patterns. This unpredictability leads network-on-chip (NoC) designers to plan for the worst-case traffic patterns, and significantly over-provision link capacities. In this paper, we provide NoC designers with an alternative statistical approach. We first present the traffic-load distribution plots (T-Plots), illustrating how much capacity over-provisioning is needed to service 90%, 99%, or 100% of all traffic patterns. We prove that in the general case, plotting T-Plots is #P-complete, and therefore extremely complex. We then show how to determine the exact mean and variance of the traffic load on any edge, and use these to provide Gaussian-based models for the T-Plots, as well as guaranteed performance bounds. Finally, we use T-Plots to reduce the network power consumption by providing an efficient capacity allocation algorithm with predictable performance guarantees.
UR - http://www.scopus.com/inward/record.url?scp=44149117274&partnerID=8YFLogxK
U2 - 10.1109/NOCS.2008.4492736
DO - 10.1109/NOCS.2008.4492736
M3 - Conference contribution
AN - SCOPUS:44149117274
SN - 0769530982
SN - 9780769530987
T3 - Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008
SP - 171
EP - 180
BT - Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008
T2 - 2nd IEEE International Symposium on Networks-on-Chip, NOCS 2008
Y2 - 7 April 2008 through 11 April 2008
ER -