Statistical approach to NoC design

Itamar Cohen, Ori Rottenstreich, Isaac Keslassy

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Chip multiprocessors (CMPs) combine increasingly many general-purpose processor cores on a single chip. These cores run several tasks with unpredictable communication needs, resulting in uncertain and often-changing traffic patterns. This unpredictability leads network-on-chip (NoC) designers to plan for the worst-case traffic patterns, and significantly over-provision link capacities. In this paper, we provide NoC designers with an alternative statistical approach. We first present the traffic-load distribution plots (T-Plots), illustrating how much capacity over-provisioning is needed to service 90%, 99%, or 100% of all traffic patterns. We prove that in the general case, plotting T-Plots is #P-complete, and therefore extremely complex. We then show how to determine the exact mean and variance of the traffic load on any edge, and use these to provide Gaussian-based models for the T-Plots, as well as guaranteed performance bounds. Finally, we use T-Plots to reduce the network power consumption by providing an efficient capacity allocation algorithm with predictable performance guarantees.

Original languageEnglish
Title of host publicationProceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008
Pages171-180
Number of pages10
DOIs
StatePublished - 28 May 2008
Externally publishedYes
Event2nd IEEE International Symposium on Networks-on-Chip, NOCS 2008 - Newcastle upon Tyne, United Kingdom
Duration: 7 Apr 200811 Apr 2008

Publication series

NameProceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008

Conference

Conference2nd IEEE International Symposium on Networks-on-Chip, NOCS 2008
Country/TerritoryUnited Kingdom
CityNewcastle upon Tyne
Period7/04/0811/04/08

ASJC Scopus subject areas

  • Computer Science (all)

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