TY - GEN
T1 - STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications
AU - Garzon, Esteban
AU - Yavits, Leonid
AU - Teman, Adam
AU - Lanuzza, Marco
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023/1/1
Y1 - 2023/1/1
N2 - This work explores non-volatile (NV) embedded memories implemented by spin-transfer torque magnetic random access memories (STT-MRAMs). Our designs are based on state-of-the-art perpendicular magnetic tunnel junctions (MTJs) along with a commercial 65 nm planar CMOS Bulk technology node, both operating at the liquid nitrogen temperature, 77 K. We evaluate the impact of cooling down to 77 K of the STT-MRAMs based on single- and double-barrier MTJ (SMTJ and DMTJ), and DMTJ with the relaxed non-volatility. All NV designs were benchmarked against the six-transistor SRAM (6T-SRAM) baseline. Simulation analysis relies on a 512 kB cache memory operating at 77 K. Overall, results show that the implementation of STT-MRAMs with DMTJ devices, and in particular when using the non-volatility approach by reducing the cross-section area, excel in terms of energy consumption, leading to energy savings for write/read access of about 35%/54%. This saving is obtained while also dissipating less leakage power and requiring a smaller bitcell footprint. Moreover, it presents reduced write latency overhead (as much as 1.9× lower), at the expense of increased read latency and reduced sensing margins of about 1.8× and 88%, respectively. The results suggest that STT-MRAM technology can be a solid alternative for energy-efficient cryogenic memory applications.
AB - This work explores non-volatile (NV) embedded memories implemented by spin-transfer torque magnetic random access memories (STT-MRAMs). Our designs are based on state-of-the-art perpendicular magnetic tunnel junctions (MTJs) along with a commercial 65 nm planar CMOS Bulk technology node, both operating at the liquid nitrogen temperature, 77 K. We evaluate the impact of cooling down to 77 K of the STT-MRAMs based on single- and double-barrier MTJ (SMTJ and DMTJ), and DMTJ with the relaxed non-volatility. All NV designs were benchmarked against the six-transistor SRAM (6T-SRAM) baseline. Simulation analysis relies on a 512 kB cache memory operating at 77 K. Overall, results show that the implementation of STT-MRAMs with DMTJ devices, and in particular when using the non-volatility approach by reducing the cross-section area, excel in terms of energy consumption, leading to energy savings for write/read access of about 35%/54%. This saving is obtained while also dissipating less leakage power and requiring a smaller bitcell footprint. Moreover, it presents reduced write latency overhead (as much as 1.9× lower), at the expense of increased read latency and reduced sensing margins of about 1.8× and 88%, respectively. The results suggest that STT-MRAM technology can be a solid alternative for energy-efficient cryogenic memory applications.
KW - 77 K
KW - cryogenic
KW - double-barrier MTJ (DMTJ)
KW - embedded memory
KW - energy-efficient
KW - Magnetic tunnel junction (MTJ)
KW - single-barrier MTJ (SMTJ)
KW - STT-MRAM
UR - http://www.scopus.com/inward/record.url?scp=85159707193&partnerID=8YFLogxK
U2 - 10.1109/LASCAS56464.2023.10108316
DO - 10.1109/LASCAS56464.2023.10108316
M3 - Conference contribution
AN - SCOPUS:85159707193
T3 - LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings
BT - LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings
A2 - Huerta, Monica Karel
PB - Institute of Electrical and Electronics Engineers
T2 - 14th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2023
Y2 - 27 February 2023 through 3 March 2023
ER -
