Subthreshold dual mode logic

Asaf Kaizerman, Sagi Fisher, Alexander Fish

Research output: Contribution to journalArticlepeer-review

32 Scopus citations

Abstract

In this brief, we introduce a novel low-power dual mode logic (DML) family, designed to operate in the subthreshold region. The proposed logic family can be switched between static and dynamic modes of operation according to system requirements. In static mode, the DML gates feature very low-power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. This is achieved with a simple and intuitive design concept. SPICE and Monte Carlo simulations compare performance, power dissipation, and robustness of the proposed DML gates to their CMOS and domino counterparts in the 80-nm process. Measurements of an 80-nm test chip are presented in order to prove the proposed concept.

Original languageEnglish
Article number6220906
Pages (from-to)979-983
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume21
Issue number5
DOIs
StatePublished - 1 Jan 2013
Externally publishedYes

Keywords

  • Dual mode logic (DML)
  • low power
  • subthreshold

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