Synthesizing hashing circuits

Benjamin Arazi

doi:10.1109/MWSCAS.2005.1594041

Synthesizing hashing circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An approach for hardware synthesis of hashing transformations is presented, where the prescribed features that define a secure transformation are enforced by the design rules. This approach is fundamentally different from that adopted in implementations like SHA-1 or MD5, which are based on first devising an algorithm, and then analyzing it, with possible further modifications until arriving at a satisfactory performance that does not necessarily have solid theoretical foundations.

Original language	English
Title of host publication	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Pages	67-70
Number of pages	4
DOIs	https://doi.org/10.1109/MWSCAS.2005.1594041
State	Published - 1 Dec 2005
Externally published	Yes
Event	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 - Cincinnati, OH, United States Duration: 7 Aug 2005 → 10 Aug 2005

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	2005
ISSN (Print)	1548-3746

Conference

Conference	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Country/Territory	United States
City	Cincinnati, OH
Period	7/08/05 → 10/08/05

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/MWSCAS.2005.1594041

Cite this

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title = "Synthesizing hashing circuits",

abstract = "An approach for hardware synthesis of hashing transformations is presented, where the prescribed features that define a secure transformation are enforced by the design rules. This approach is fundamentally different from that adopted in implementations like SHA-1 or MD5, which are based on first devising an algorithm, and then analyzing it, with possible further modifications until arriving at a satisfactory performance that does not necessarily have solid theoretical foundations.",

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year = "2005",

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doi = "10.1109/MWSCAS.2005.1594041",

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Arazi, B 2005, Synthesizing hashing circuits. in 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005., 1594041, Midwest Symposium on Circuits and Systems, vol. 2005, pp. 67-70, 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005, Cincinnati, OH, United States, 7/08/05. https://doi.org/10.1109/MWSCAS.2005.1594041

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AB - An approach for hardware synthesis of hashing transformations is presented, where the prescribed features that define a secure transformation are enforced by the design rules. This approach is fundamentally different from that adopted in implementations like SHA-1 or MD5, which are based on first devising an algorithm, and then analyzing it, with possible further modifications until arriving at a satisfactory performance that does not necessarily have solid theoretical foundations.

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M3 - Conference contribution

AN - SCOPUS:33847147691

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BT - 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005

T2 - 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005

Y2 - 7 August 2005 through 10 August 2005

ER -

Synthesizing hashing circuits

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

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