TY - GEN
T1 - TEMPO
T2 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
AU - Munk, Tom
AU - Kugler, Hillel
AU - Maori, Ofir
AU - Teman, Adam
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/4/1
Y1 - 2019/4/1
N2 - Communication rates of high-throughput network switches cause heat dissipation that can harm both performance and system reliability. Therefore, these systems integrate an aggressive cooling subsystem, often based on the operation of power-hungry fans at high-speeds to maintain a low ambient temperature. However, this may lead to both a high-degree of power waste and unacceptable acoustic levels. In this paper, we propose TEMPO, a thermal-efficient management scheme for system cooling with minimal fan power consumption and noise production, based on a straightforward, simple to apply algorithm. Tempo was applied to a Mellanox switch providing as much as a 30% power reduction and a 20% sound power reduction compared to the previously available commercial firmware.
AB - Communication rates of high-throughput network switches cause heat dissipation that can harm both performance and system reliability. Therefore, these systems integrate an aggressive cooling subsystem, often based on the operation of power-hungry fans at high-speeds to maintain a low ambient temperature. However, this may lead to both a high-degree of power waste and unacceptable acoustic levels. In this paper, we propose TEMPO, a thermal-efficient management scheme for system cooling with minimal fan power consumption and noise production, based on a straightforward, simple to apply algorithm. Tempo was applied to a Mellanox switch providing as much as a 30% power reduction and a 20% sound power reduction compared to the previously available commercial firmware.
UR - http://www.scopus.com/inward/record.url?scp=85068619577&partnerID=8YFLogxK
U2 - 10.1109/VLSI-DAT.2019.8741684
DO - 10.1109/VLSI-DAT.2019.8741684
M3 - Conference contribution
AN - SCOPUS:85068619577
T3 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
BT - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
PB - Institute of Electrical and Electronics Engineers
Y2 - 22 April 2019 through 25 April 2019
ER -